公开(公告)号：US20020080898A1

公开(公告)日：2002-06-27

申请号：US10085071

申请日：2002-03-01

Applicant: Broadcom Incorporated

Inventor： Oscar Agazzi ,  Venugopal Gopinathan

IPC: H04L007/00

CPC classification number: H04L25/03006 ,  H03M1/0604 ,  H03M1/0607 ,  H03M1/0609 ,  H03M1/0624 ,  H03M1/0836 ,  H03M1/1215 ,  H04B10/6933 ,  H04B10/697 ,  H04B10/6971 ,  H04L7/0054 ,  H04L7/0062 ,  H04L7/0337 ,  H04L25/03057 ,  H04L25/03133 ,  H04L25/03159 ,  H04L25/03203 ,  H04L2025/03445

Abstract: Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (nullADCnull) and/or a digital signal processor (nullDSPnull) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. The separate timing recovery loops can be used to compensate for timing phase errors in the clock generation circuit that are different for each path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. The separate AGC loops can be used to compensate for gain errors on a path-by-path basis. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. The separate offset compensation loops can be used to independently compensate for offsets that are different for each path. In an embodiment the present invention is implemented as a multi-channel receiver that receives a plurality of data signals. In an embodiment, one or more of the following types of equalization are performed, alone and/or in various combinations with one another: Viterbi equalization; feed-forward equalization (nullFFEnull); and/or decision feed-back equalization (nullDFEnull).

Abstract translation: 用于接收数据信号的基于数字信号处理的方法和系统包括并行接收机，多信道接收机，定时恢复方案，并且不限于均衡方案。 本发明被实现为多路径并行接收机，其中使用平行路径来实现模数转换器（“ADC”）和/或数字信号处理器（“DSP”），该路径以比 接收数据信号。 在一个实施例中，根据本发明的基于并行DSP的接收机包括用于每个ADC路径的单独的定时恢复环路。 单独的定时恢复环路可用于补偿时钟发生电路中针对每个路径不同的定时相位误差。 在一个实施例中，并行基于DSP的接收机包括用于每个ADC路径的单独的自动增益控制（AGC）环路。 单独的AGC环路可用于补偿逐个路径上的增益误差。 在一个实施例中，并行基于DSP的接收机包括用于每个ADC路径的单独的偏移补偿环路。 单独的偏移补偿回路可用于独立补偿每个路径不同的补偿。 在一个实施例中，本发明被实现为接收多个数据信号的多信道接收机。 在一个实施例中，独立地和/或彼此以各种组合执行以下类型的均衡中的一个或多个：维特比均衡; 前馈均衡（“FFE”）; 和/或判决反馈均衡（“DFE”）。