-
1.发明授权Peripheral controller comprising first messaging unit for communication with first OS driver and second messaging unit for communication with second OS driver for mass-storage peripheral 失效外围控制器包括用于与第一OS驱动器通信的第一消息单元和用于与用于大容量存储外设的第二OS驱动器通信的第二消息单元
公开(公告)号：US6154789A
公开(公告)日：2000-11-28
申请号：US97409
申请日：1998-06-15
CPC分类号： G06F13/385 , G06F13/102
摘要： An embodiment of the present invention provides a peripheral controller for coupling a mass storage peripheral to a computer system. In a disclosed embodiment the peripheral controller is a disk array controller programmed for RAID. The peripheral controller includes a first messaging unit (FMU), a second messaging unit (SMU), and a peripheral interface which are connected by a local bus. The FMU responds to messages from a first operating system driver. The SMU responds to messages from a different second operating system driver. In one embodiment, the FMU responds to commands from the first operating system driver which is non-standard. In another embodiment, the SMU responds to commands from the second operating system driver which is compatible with the I2O standard. In the disclosed embodiment, the peripheral interface controls mass storage peripherals in response to messages sent to the FMU or the SMU.
摘要翻译： 本发明的实施例提供了一种用于将大容量存储外围设备耦合到计算机系统的外围控制器。 在公开的实施例中，外围控制器是针对RAID编程的盘阵列控制器。 外围控制器包括通过本地总线连接的第一消息接发单元（FMU），第二通信单元（SMU）和外围接口。 FMU响应来自第一个操作系统驱动程序的消息。 SMU响应来自不同第二操作系统驱动程序的消息。 在一个实施例中，FMU响应来自非标准的第一操作系统驱动器的命令。 在另一实施例中，SMU响应来自与I2O标准兼容的第二操作系统驱动器的命令。 在所公开的实施例中，外围接口响应于发送到FMU或SMU的消息来控制大容量存储外设。
-
2.发明授权Technique for hot plugging a peripheral controller card containing PCI and SCSI buses on a single connector into a host system board 失效将单个连接器上包含PCI和SCSI总线的外围控制器卡插入主机系统板的技术
公开(公告)号：US6061752A
公开(公告)日：2000-05-09
申请号：US97493
申请日：1998-06-15
CPC分类号： G06F13/409
摘要： An embodiment of the present invention discloses a technique that allows hot plugging a peripheral controller card, containing both a local bus and a peripheral bus on a single connector, into a host system board containing a host system bus and a host I/O bus. When mating the peripheral controller card to the host system board a local device power supply (LDPS) is inactive, a peripheral device power bus (PDPB) is powered, and signal lines of a peripheral device are maintained in a high impedance state. Following a delay after the mating, the LDPS is activated by the host operating system (OS). Following the activation of the LDPS, the host system bus is coupled to the single connector through switches that are under OS control. In response to the activation of the LDPS, the signal lines of the peripheral device are enabled.In a disclosed embodiment the peripheral controller card is a disk array controller card, the local bus is a PCI bus, and the peripheral bus is a SCSI bus. In one embodiment the disk array controller card is coupled to a mass storage peripheral and in another embodiment is programmed for RAID. An advantage of an embodiment of the present invention is that a PCI bus and a SCSI bus are carried on a single peripheral connector which provides cable management and readily allows hot plugging a redundant peripheral controller card into the host system board.
摘要翻译： 本发明的实施例公开了一种技术，其允许将包含本地总线和外围总线的外围控制器卡热插拔到单个连接器上，并将其插入到包含主机系统总线和主机I / O总线的主机系统板中。 外围设备电源总线（PDPB）为外部设备电源总线（PDPB）供电时，外围设备的信号线保持在高阻抗状态。 在配对后延时，LDPS由主机操作系统（OS）激活。 在激活LDPS之后，主机系统总线通过处于OS控制下的开关耦合到单个连接器。 响应于LDPS的激活，外围设备的信号线被使能。 在公开的实施例中，外围控制器卡是磁盘阵列控制卡，局部总线是PCI总线，外围总线是SCSI总线。 在一个实施例中，磁盘阵列控制器卡耦合到大容量存储外围设备，并且在另一个实施例中被编程用于RAID。 本发明的一个实施例的优点在于，PCI总线和SCSI总线被承载在提供电缆管理的单个外围连接器上，并且容易地将冗余外围控制器卡热插拔到主机系统板中。
-
3.发明授权Hiding peripheral memory transactions on a local bus within a peripheral controller from a host system bus 失效在外部控制器中的本地总线上从主机系统总线隐藏外设存储器事务
公开(公告)号：US6128686A
公开(公告)日：2000-10-03
申请号：US97408
申请日：1998-06-15
CPC分类号： G06F13/404
摘要： An embodiment of the present invention discloses a technique for concealing a peripheral memory transaction on a local bus within a peripheral controller from a host system bus. In the preferred embodiment both the local bus and the host system bus are PCI buses. The technique is implemented when a peripheral memory transaction is detected on the local bus. In a disclosed embodiment, the peripheral memory transaction is detected by monitoring command and byte enables (CBEs) and five upper address bits (AD[31::27]) of the local bus. A peripheral memory transaction is indicated when a memory transaction on the local bus is directed to an upper 128 MB of 4 GB host memory. When a memory transaction is detected to the upper 128 MB of memory the transaction is intercepted. The interception is accomplished by blocking the CBEs on the local bus from a peripheral interface.The peripheral interface in the preferred embodiment is a standard PCI--PCI bridge which couples the local bus to the host system bus. After being intercepted, the CBEs are recoded so that the memory transaction does not appear on the host system bus. In the disclosed embodiment the memory CBEs are recoded to reserved CBEs of the same parity as the memory CBEs. An advantage of the present invention is that a standard PCI--PCI bridge can be utilized to interface the peripheral controller to the host system bus.
摘要翻译： 本发明的实施例公开了一种用于在主机系统总线上隐藏外围控制器内的本地总线上的外围存储器交易的技术。 在优选实施例中，本地总线和主机系统总线都是PCI总线。 当在本地总线上检测到外围存储器事务时，实现该技术。 在公开的实施例中，通过本地总线的监视命令和字节使能（CBE）和五个高位地址位（AD [31 :: 27]）来检测外围存储器事务。 当本地总线上的存储器事务定向到高达128 MB的4 GB主机内存时，会指示外设存储器事务。 当内存事务检测到高128 MB的内存时，事务被拦截。 截取通过从外围接口阻止局部总线上的CBE来实现。 优选实施例中的外围接口是将本地总线耦合到主机系统总线的标准PCI-PCI桥。 被拦截后，CBE被重新编码，使得内存事务不会出现在主机系统总线上。 在所公开的实施例中，存储器CBE被重新编码为与存储器CBE相同奇偶性的保留CBE。 本发明的一个优点是可以使用标准PCI-PCI桥接器来将外围控制器与主机系统总线相连接。
-
4.发明授权Secondary channel for command information for fibre channel system interface bus 失效光纤通道系统接口总线命令信息的二级通道
公开(公告)号：US5848251A
公开(公告)日：1998-12-08
申请号：US692516
申请日：1996-08-06
CPC分类号： G06F13/4278
摘要： The present invention relates to a secondary channel for a point-to-point burst style bus associated with a computer system. The point-to-point bus may originate as a standardized bus from a fibre channel controller. The point-to-point bus connects to another circuit which may be a bridge circuit, a minicomputer or a peripheral device. A secondary channel is also connected to the point-to-point bus and is adapted to share the bus by receiving information having predetermined addresses. The information recieved by the secondary channel can be stored in a memory that is shared with a processor. Command/control information can be extracted from the point-to-point bus before data is transferred through the bridge circuit in order to allow the data to be acted on more quickly by processing/storage devices since the control data was already made available to the storage devices via the secondary channel.
摘要翻译： 本发明涉及一种与计算机系统相关联的点对点突发样式总线的辅助信道。 点对点总线可以作为来自光纤通道控制器的标准化总线发起。 点对点总线连接到另一个可能是桥接电路，小型计算机或外围设备的电路。 辅助信道也连接到点对点总线，并且适于通过接收具有预定地址的信息来共享总线。 辅助频道接收到的信息可以存储在与处理器共享的存储器中。 在通过桥接电路传输数据之前，可以从点对点总线提取命令/控制信息，以便通过处理/存储设备更快速地执行数据，因为控制数据已经可用于 存储设备通过辅助通道。
-
5.发明授权System and method for electrically isolating a device from higher voltage devices 失效将器件与较高电压器件电隔离的系统和方法公开(公告)号：US06205500B1
公开(公告)日：2001-03-20
申请号：US08936208
申请日：1997-09-24
IPC分类号： G06I1300
CPC分类号： G06F13/4068 , Y10T307/675
摘要： An isolation system and method that electrically couples a device to a bus during cycles associated with or accessing the device, but otherwise isolates the device from the bus. The isolation system includes an isolation device coupled to the device and to the bus that includes an enable input adapted to receive an enable signal, where the isolation device electrically couples the device to said bus while the enable signal is asserted, but otherwise electrically isolates the device from the bus. The isolation system further includes enable logic that detects cycles on the bus and provides the enable signal to the enable input of the isolation device during a cycle if the cycle is associated with the device. The isolation device may comprise a bus switch, one or more discrete isolating devices such as bipolar transistors, field-effect transistors, or any other suitable device for isolating a device from the bus. Generally, the enable logic may comprise decode logic that decodes an address on the bus during the bus cycle to determine if the address corresponds to an address of the device. Decode logic is usefuil for decoding a memory cycle on the bus for accessing a low voltage memory device, which is otherwise isolated from the bus.
摘要翻译： 一种隔离系统和方法，在与设备相关联或访问设备的周期期间将设备电耦合到总线，但是将设备与总线隔离。 隔离系统包括耦合到装置和总线的隔离装置，该隔离装置包括适于接收使能信号的使能输入，其中隔离装置在使能信号被断言时将该装置电耦合到所述总线，而另外电隔离 设备从公共汽车。 隔离系统还包括启用逻辑，其检测总线上的周期，并且如果周期与设备相关联，则在一个周期期间将启用信号提供给隔离设备的使能输入。 隔离装置可以包括总线开关，一个或多个离散隔离装置，例如双极晶体管，场效应晶体管或用于将装置与总线隔离的任何其它合适的装置。 通常，使能逻辑可以包括在总线周期期间解码总线上的地址以确定地址是否对应于设备的地址的解码逻辑。 解码逻辑是用于解码总线上的存储器周期的用途，用于访问与总线隔离的低电压存储器件。
-
6.发明授权Nonmaskable interrupt workaround for a single exception interrupt handler processor 失效单个异常中断处理程序处理器的不可屏蔽中断解决方法公开(公告)号：US06732298B1
公开(公告)日：2004-05-04
申请号：US09628747
申请日：2000-07-31
IPC分类号： H02H305
CPC分类号： G06F11/0772 , G06F11/0724 , G06F11/0727 , G06F11/0745
摘要： A system and method is disclosed for debugging of a hardware board that includes a processor with only a single level of interrupts that are either all enabled or all disabled. The processor does not implement nonmaskable interrupts. The processor on the board contains a machine check exception (MCP) input line that permits implementation of a nonmaskable pseudo-interrupt for debugging of the hardware board. The nonmaskable pseudo-interrupt informs the processor of a debug request even when all device interrupts in the interrupt processor are disabled. A processor-to-bus bridge connected to the processor on the hardware board contains a critical interrupt register. Test equipment connected to the processor-to-bus bridge sets a bit in the critical interrupt register for requesting the nonmaskable pseudo-interrupt, the processor-to-bus bridge reading the bit in the critical interrupt register to determine whether a nonmaskable pseudo interrupt debug request has occurred. The processor-to-bus bridge asserts the MCP input line of the processor after determining that the test equipment has requested the nonmaskable pseudo-interrupt. The processor then executes handler software that communicates with the test equipment to debug the hardware board.
摘要翻译： 公开了一种用于调试硬件板的系统和方法，该硬件板包括仅具有单个级别的中断的处理器，所述中断全部被使能或全部禁用。 处理器不实现不可屏蔽的中断。 电路板上的处理器包含机器检查异常（MCP）输入线，允许执行不可屏蔽的伪中断来调试硬件电路板。 即使中断处理器中的所有设备中断被禁用，不可屏蔽伪中断也会通知处理器调试请求。 连接到硬件板上的处理器的处理器到总线桥包含一个关键的中断寄存器。 连接到处理器到总线桥的测试设备在关键中断寄存器中设置一点请求不可屏蔽的伪中断，处理器到总线桥读取关键中断寄存器中的位，以确定是否存在不可屏蔽的伪中断调试 发出请求。 在确定测试设备已经请求不可屏蔽的伪中断之后，处理器到总线桥断言处理器的MCP输入线。 然后，处理器执行与测试设备通信的处理程序软件，以调试硬件板。
-
公开(公告)号：US07644168B2
公开(公告)日：2010-01-05
申请号：US11180145
申请日：2005-07-13
CPC分类号： G06F13/387
摘要： Systems and methodologies associated with providing additional functionality to a conventional SAS expander are described. One exemplary SAS expander embodiment includes logic for selectively performing source identifier checking for frames received at the SAS expander. The logic may also facilitate selectively performing explicit route checking for frames received at the SAS expander. In one example, the logic may also facilitate selectively providing VLAN-like services to devices connected to the SAS expander.
摘要翻译： 描述了与常规SAS扩展器提供附加功能相关联的系统和方法。 一个示例性的SAS扩展器实施例包括用于选择性地执行在SAS扩展器处接收的帧的源标识符检查的逻辑。 逻辑还可以有助于选择性地执行在SAS扩展器处接收到的帧的显式路由检查。 在一个示例中，逻辑还可以有助于选择性地向连接到SAS扩展器的设备提供类VLAN的服务。
-
8.发明授权Disk array controller having internal protocol for sending address/transfer count information during first/second load cycles and transferring data after receiving an acknowldgement 失效磁盘阵列控制器具有用于在第一/第二加载周期期间发送地址/传送计数信息的内部协议，并且在接收到确认之后传送数据
公开(公告)号：US5469548A
公开(公告)日：1995-11-21
申请号：US263018
申请日：1994-06-20
CPC分类号： G06F3/0601 , G06F12/0866 , G06F13/124 , G06F2003/0692
摘要： A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master. The ADAC is connected to transfer buffer RAM. The protocol of the internal data bus provides for a cycle to load a host memory address into the bus slave, to provide transfer count information and slave specific information and for a series of data transfer cycles. The local processor is connected to the EISA bus master and the ADAC to control operations and to provide certain information. The ADAC is controlled by structures referred to as command descriptor blocks (CDBs). Each CDB includes information which describes the various addresses, control bits and functional bits used by the ADAC to perform its transfer operations. The local processor directly writes and deposits data forming a CDB into the transfer buffer RAM. The ADAC obtains the CDB, loads the data into registers and then performs operations according to the information contained in these registers until a transfer is done. The ADAC itself performs operations, including automatic stripe scattering and gathering to develop contiguous host memory fields from striped array data. A series of CDBs can be chained so that a complex series of tasks can be developed. In one variation a string of CDBs is developed to transfer data but some data is transferred to the bit bucket, while other data is actually transferred.
摘要翻译： 一种磁盘阵列控制器板，其使用作为其内部数据总线上的从机的EISA总线主机，以允许先进的驱动器阵列控制器芯片（ADAC）作为主机操作。 ADAC连接到传输缓冲RAM。 内部数据总线的协议提供了将主机存储器地址加载到总线从站中的周期，以提供传输计数信息和从属特定信息以及一系列数据传输周期。 本地处理器连接到EISA总线主控和ADAC控制操作并提供某些信息。 ADAC由称为命令描述符块（CDB）的结构控制。 每个CDB包括描述ADAC用于执行其传送操作的各种地址，控制位和功能位的信息。 本地处理器直接将形成CDB的数据写入并存储到传送缓冲器RAM中。 ADAC获得CDB，将数据加载到寄存器中，然后根据这些寄存器中包含的信息执行操作，直到传输完成。 ADAC本身执行操作，包括自动条纹散射和收集，以从条形阵列数据开发连续的主机内存字段。 一系列CDB可以链接，以便可以开发一系列复杂的任务。 在一个变化中，开发了一串CDB来传输数据，但是一些数据被传送到比特桶，而其他数据被实际传输。
-
9.发明授权Apparatus and method for developing wait states during addressing operation by using unused address bits 失效通过使用未使用的地址位在寻址操作期间发展等待状态的装置和方法
公开(公告)号：US5253355A
公开(公告)日：1993-10-12
申请号：US612132
申请日：1990-11-13
申请人： Thomas W. Grieff
发明人： Thomas W. Grieff
CPC分类号： G06F13/4243
摘要： An apparatus and method for providing wait states using address bits not used in the device address decode. The upper address bits of a computer system are not used for peripheral and memory device decoding purposes. The unused bits are driven to indicate the desired number of wait states to be developed for each selected device, while still allowing a normal decode of the devices. Wait state and ready logic is provided which allows each device address to be assigned one of several possible wait state lengths by driving the most significant bits of the address. The address decode based wait state determination is overridden for RAM operations, and followed for ROM and peripheral operations.
-
公开(公告)号：US5150465A
公开(公告)日：1992-09-22
申请号：US815900
申请日：1991-12-31
CPC分类号： G06F3/0601 , G06F13/4226 , G06F2003/0692
摘要： An interface between a CPU bus and peripheral device such as a standard embedded controller disk drive uses either a dedicated, I/O mapped register set for control and status communication between the host CPU and the disk controller, or an alternate "flex mode" protocol which allows the drive to be used with great versatility in a wide variety of systems. This alternate "flex mode" protocol does not require changes to the hardware definition of the drive interface, but instead uses the data port to transfer information blocks to set up a subsequent data transfer through this port.
摘要翻译： CPU总线和外围设备（如标准嵌入式控制器磁盘驱动器）之间的接口使用专用I / O映射寄存器集，用于主机CPU和磁盘控制器之间的控制和状态通信，或者使用备用的“flex模式”协议 这允许驱动器在各种系统中具有极大的通用性。 这种备用的“灵活模式”协议不需要更改驱动器接口的硬件定义，而是使用数据端口传输信息块，以建立通过此端口的后续数据传输。
-
-
-
-
-
-
-
-
-
搜索结果
16 条记录 (耗时 0.023 秒)
