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1.发明授权公开(公告)号：US07391270B2
公开(公告)日：2008-06-24
申请号：US11086039
申请日：2005-03-22
IPC分类号： H03L7/00
CPC分类号： H03L7/1974
摘要： A phase locked loop is disclosed and includes a frequency divider circuit with a settable division ratio in a feedback path. The division ratio is produced using a control circuit which, besides an input for supplying the integer and fractional components for the frequency division ratio which is to be set, includes an input for supplying a phase correction signal. To produce the phase correction signal, the phase locked loop further includes a phase correction apparatus. The phase correction signal preferably contains a signal component with an exponential profile, and is supplied to the control circuit for producing a frequency division ratio for the frequency divider circuit such that it compensates for a phase drift in the output signal from the voltage controlled oscillator in the phase locked loop.
摘要翻译： 公开了一种锁相环，并且包括在反馈路径中具有可设置的分频比的分频器电路。 使用控制电路产生分频比，除了用于提供要被设置的分频比的整数和分数分量的输入外，还包括用于提供相位校正信号的输入。 为了产生相位校正信号，锁相环还包括相位校正装置。 相位校正信号优选地包含具有指数曲线的信号分量，并且被提供给控制电路以产生分频器电路的分频比，使得其补偿来自压控振荡器的输出信号中的相位漂移 锁相环。
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公开(公告)号：US07586994B2
公开(公告)日：2009-09-08
申请号：US11055740
申请日：2005-02-10
IPC分类号： H04L27/20
CPC分类号： H04L27/0014 , H04L2027/0016 , H04L2027/0018
摘要： The invention provides an interface apparatus for data recovery which supplies an analog signal (applied to the input and containing data in line with a coding) having a first component and a second component to a signal processor. From this, the signal processor produces a continuous, demodulated data stream. The data stream is supplied to a connected delay unit, whose output is designed to provide the stored data symbols and whose delay in provision can be set by a signal at a control input. The interface allows a digital modulator to be connected to an analog I/Q interface on a baseband unit.
摘要翻译： 本发明提供了一种用于数据恢复的接口装置，其向信号处理器提供具有第一分量和第二分量的模拟信号（应用于输入并包含符合编码的数据）。 由此，信号处理器产生连续的解调数据流。 数据流被提供给连接的延迟单元，其输出被设计为提供所存储的数据符号，并且可以通过控制输入端的信号设置其提供延迟。 该接口允许将数字调制器连接到基带单元上的模拟I / Q接口。
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3.发明申请公开(公告)号：US20090305649A1
公开(公告)日：2009-12-10
申请号：US12543396
申请日：2009-08-18
IPC分类号： H04B1/40
CPC分类号： H04B1/30
摘要： A control circuit may be provided. In this case, an output of the control circuit is connected to a control input of a signal generator. Depending on internal signals which identify an operating state of a signal processing device, the control circuit generates a regulating signal at the output. The operating point of the signal generator is thereby set in such a way that a current consumption of the signal processing device is reduced, so that the signal quality is ensured in a sufficient manner.
摘要翻译： 可以提供控制电路。 在这种情况下，控制电路的输出连接到信号发生器的控制输入。 根据识别信号处理装置的操作状态的内部信号，控制电路在输出端产生调节信号。 因此，信号发生器的工作点被设置为使得信号处理装置的电流消耗减小，从而以充分的方式确保信号质量。
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4.发明授权Phase-locked loop with a pulse generator, and method for operating the phase-locked loop 有权带有脉冲发生器的锁相环，以及操作锁相环的方法公开(公告)号：US07199672B2
公开(公告)日：2007-04-03
申请号：US11127621
申请日：2005-05-12
申请人： Christian Münker , Markus Scholz
发明人： Christian Münker , Markus Scholz
IPC分类号： H03L7/00
CPC分类号： H03L7/0891 , H03L7/18
摘要： The phase-locked loop has a pulse generator has a phase detector which is intended to compare a reference signal with an oscillator signal, and a detector output for tapping off a phase comparison signal. The pulse generator is used to produce a pulse-width-modulated pulse signal and has a generator output, from which the pulse-width-modulated pulse signal is tapped off. A selection unit is furthermore provided and is connected, on the input side, to the detector output and to the generator output, and is designed in such a manner that either the phase comparison signal or the pulse signal can be tapped off from an output of the selection unit using a control signal applied to a control input of the selection unit.
摘要翻译： 锁相环具有脉冲发生器，其具有用于将参考信号与振荡器信号进行比较的相位检测器和用于抽出相位比较信号的检测器输出。 脉冲发生器用于产生脉冲宽度调制脉冲信号，并具有发生器输出，脉冲宽度调制脉冲信号从该脉冲信号被分接。 此外，提供选择单元，并且在输入侧连接到检测器输出和发生器输出，并且被设计成使得相位比较信号或脉冲信号可以从 所述选择单元使用施加到所述选择单元的控制输入的控制信号。
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5.发明授权Phase locked loop circuit with a tunable oscillator and an independent frequency converter and frequency counter 有权具有可调振荡器和独立变频器和频率计数器的锁相环电路公开(公告)号：US07154342B2
公开(公告)日：2006-12-26
申请号：US11212422
申请日：2005-08-26
申请人： Christian Münker , Markus Scholz
发明人： Christian Münker , Markus Scholz
CPC分类号： H03K23/68 , H03K21/12 , H03K23/662 , H03L7/099 , H03L7/10 , H03L7/187 , H03L7/1974
摘要： A phase regulating arrangement or circuit is disclosed, in which, in addition to a frequency divider, which is arranged in the feedback path of the PLL and, provision is made of a further frequency counter. The frequency counter is configured to be readable and is likewise connected to the oscillator output. The frequency counter drives a control unit that selects a desired frequency band of a multiband oscillator. The phase regulating arrangement or circuit described enables very fast settling in conjunction with low phase noise and good integration possibilities.
摘要翻译： 公开了一种相位调节装置或电路，其中除了配置在PLL的反馈路径中的分频器之外，还提供另外的频率计数器。 频率计数器被配置为可读，并且同样连接到振荡器输出。 频率计数器驱动选择多频振荡器的期望频带的控制单元。 所描述的相位调节装置或电路能够实现与低相位噪声和良好集成可能性相结合的非常快速的稳定。
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6.发明授权Signal processing device and method for operating a signal processing device 失效用于操作信号处理装置的信号处理装置和方法公开(公告)号：US07627299B2
公开(公告)日：2009-12-01
申请号：US11342101
申请日：2006-01-27
IPC分类号： H04B1/06
CPC分类号： H04B1/30
摘要： A signal processing device implemented in a semiconductor body includes a frequency conversion device and a converter connected to the frequency conversion device. The conversion device is coupled by a terminal to a terminal on the surface of the semiconductor body. One terminal of the converter is connected to a terminal node of the signal processing device. A signal generator, which is connected by its signal output to a local oscillator input of the frequency conversion device, has a control input for setting its operating point. Furthermore, a control circuit is provided. In this case, an output of the control circuit is connected to the control input of the signal generator. Depending on internal signals which identify an operating state of the signal processing device, the control circuit generates a regulating signal at the output. The operating point of the signal generator is thereby set in such a way that a current consumption of the signal processing device is reduced, so that the signal quality is ensured in a sufficient manner.
摘要翻译： 在半导体本体中实现的信号处理装置包括连接到变频装置的变频装置和转换器。 转换装置通过端子耦合到半导体本体的表面上的端子。 转换器的一个端子连接到信号处理装置的终端节点。 通过其信号输出连接到变频装置的本地振荡器输入的信号发生器具有用于设定其工作点的控制输入端。 此外，提供了一种控制电路。 在这种情况下，控制电路的输出连接到信号发生器的控制输入。 根据识别信号处理装置的工作状态的内部信号，控制电路在输出端产生调节信号。 因此，信号发生器的工作点被设置为使得信号处理装置的电流消耗减小，从而以充分的方式确保信号质量。
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7.发明授权Detection arrangement, counter unit, phase locked loop, detection method and method for generating an oscillator signal 有权检测装置，计数器单元，锁相环，检测方法和产生振荡信号的方法公开(公告)号：US07804925B2
公开(公告)日：2010-09-28
申请号：US11705924
申请日：2007-02-14
申请人： Markus Scholz , Christian Münker
发明人： Markus Scholz , Christian Münker
CPC分类号： H03K23/66 , G04F10/005 , H03K5/133 , H03L7/085 , H03L7/0995 , H03L7/193
摘要： A detection arrangement includes a counter unit which receives a first clock signal and a reference clock signal. The counter unit derives a first data word as a function of a time deviation between clock edges of the first clock signal and the reference clock signal. The detection arrangement further includes a signal processing unit to determine a phase deviation word as a function of the first data word and a second data word, the second data word based on the duration of a clock period of the reference clock signal.
摘要翻译： 检测装置包括接收第一时钟信号和参考时钟信号的计数器单元。 计数器单元根据第一时钟信号的时钟边沿与参考时钟信号之间的时间偏差来产生第一个数据字。 检测装置还包括信号处理单元，用于基于参考时钟信号的时钟周期的持续时间来确定作为第一数据字和第二数据字的函数的相位偏移字，第二数据字。
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