公开(公告)号：US20080188042A1

公开(公告)日：2008-08-07

申请号：US11777769

申请日：2007-07-13

申请人： Byeong-Jin LEE ,  Sang-Gab KIM ,  Hong-Sick PARK

发明人： Byeong-Jin LEE ,  Sang-Gab KIM ,  Hong-Sick PARK

IPC分类号： H01L21/84

CPC分类号： H01L27/1288 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

摘要： Provided is a method of manufacturing a thin film transistor panel that may reduce manufacturing costs. The method includes forming gate wires including a gate line and a gate electrode on an insulating substrate and forming data wires including source and drain electrodes, the data wires being insulated from the gate wires. The method further includes forming a passivation layer covering the gate and data wires, forming contact holes exposing the drain electrodes by etching the passivation layer, and forming a pixel electrode by depositing an indium-free transparent conductive film on the exposed drain electrode and the passivation layer and then dry etching the transparent conductive film.

摘要翻译： 提供了可以降低制造成本的薄膜晶体管面板的制造方法。 该方法包括在绝缘衬底上形成包括栅极线和栅电极的栅极线，并形成包括源极和漏极的数据线，数据线与栅极线绝缘。 该方法还包括形成覆盖栅极和数据线的钝化层，形成通过蚀刻钝化层而暴露出漏电极的接触孔，以及通过在暴露的漏电极和钝化层上沉积无铟透明导电膜来形成像素电极 然后干燥蚀刻透明导电膜。

公开(公告)号：US20080248617A1

公开(公告)日：2008-10-09

申请号：US12123858

申请日：2008-05-20

申请人： Chang-Oh JEONG ,  Hong-Sick PARK ,  Shi-Yul KIM ,  Sang-Gab KIM

发明人： Chang-Oh JEONG ,  Hong-Sick PARK ,  Shi-Yul KIM ,  Sang-Gab KIM

IPC分类号： H01L21/331

CPC分类号： G02F1/136286 ,  G02F2001/133397 ,  G02F2001/13629 ,  G02F2201/501 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/42384

摘要： A display substrate includes a base substrate, a first metal pattern, a gate insulating layer, a second metal pattern, a channel layer and a pixel electrode. The first metal pattern is formed on the base substrate, and includes a gate line and a gate electrode of a switching element. The gate insulating layer is formed on the base substrate including the first metal pattern. The second metal pattern is formed on the gate insulating layer, and includes a source electrode, a drain electrode and a source line. The channel layer is formed under the second metal pattern, and is patterned to have substantially a same side surface as a side surface of the second metal pattern. The pixel electrode is electrically connected to the drain electrode. Therefore, an afterimage on a display panel, thus improving display quality.

摘要翻译： 显示基板包括基底基板，第一金属图案，栅极绝缘层，第二金属图案，沟道层和像素电极。 第一金属图案形成在基底基板上，并且包括开关元件的栅极线和栅电极。 栅极绝缘层形成在包括第一金属图案的基底基板上。 第二金属图案形成在栅极绝缘层上，并且包括源电极，漏电极和源极线。 沟道层形成在第二金属图案之下，并且被图案化以具有与第二金属图案的侧表面大致相同的侧表面。 像素电极电连接到漏电极。 因此，在显示面板上留下余像，从而提高显示质量。

公开(公告)号：US20130146900A1

公开(公告)日：2013-06-13

申请号：US13488733

申请日：2012-06-05

申请人： Yun-Jong YEO ,  Yu-Gwang JEONG ,  Hong-Kee CHIN ,  Sang-Gab KIM ,  Jeong-Min PARK ,  Ji-Young PARK

发明人： Yun-Jong YEO ,  Yu-Gwang JEONG ,  Hong-Kee CHIN ,  Sang-Gab KIM ,  Jeong-Min PARK ,  Ji-Young PARK

IPC分类号： H01L33/62

CPC分类号： G02F1/134363 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1248 ,  H01L27/1288

摘要： A display substrate includes a base substrate, a switching element, a protecting layer, an organic layer, a first pixel electrode and a second pixel electrode. The switching element is on the base substrate, and includes a gate electrode, a source electrode and a drain electrode. The protecting layer is on the switching element, and includes a first hole exposing the drain electrode. The organic layer is on the protecting layer, and includes a second hole which exposes a side surface of the protecting layer which defines the first hole and exposes a top surface of the protecting layer which is adjacent to the side surface of the protecting layer. The first pixel electrode is on the organic layer. The second pixel electrode overlaps the first pixel electrode, and is electrically connected to the drain electrode via the first and second holes.

摘要翻译： 显示基板包括基底基板，开关元件，保护层，有机层，第一像素电极和第二像素电极。 开关元件在基底基板上，并且包括栅电极，源电极和漏电极。 保护层位于开关元件上，并且包括暴露漏电极的第一孔。 有机层位于保护层上，并且包括第二孔，其露出限定第一孔的保护层的侧表面，并露出与保护层的侧表面相邻的保护层的顶表面。 第一像素电极在有机层上。 第二像素电极与第一像素电极重叠，并且经由第一和第二孔电连接到漏电极。

公开(公告)号：US20100044717A1

公开(公告)日：2010-02-25

申请号：US12434942

申请日：2009-05-04

申请人： Seung-Ha CHOI ,  Ki-Yeup LEE ,  Sang-Gab KIM ,  Shin-Il CHOI ,  Dong-Ju YANG ,  Hong-Kee CHIN ,  Yu-Gwang JEONG ,  Ji-Young PARK ,  Dong-Hoon LEE ,  Byeong-Beom KIM

发明人： Seung-Ha CHOI ,  Ki-Yeup LEE ,  Sang-Gab KIM ,  Shin-Il CHOI ,  Dong-Ju YANG ,  Hong-Kee CHIN ,  Yu-Gwang JEONG ,  Ji-Young PARK ,  Dong-Hoon LEE ,  Byeong-Beom KIM

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/458 ,  H01L27/124 ,  H01L29/4908

摘要： After forming a signal line including aluminum, an upper layer of an oxide layer including aluminum that covers the signal line is formed in the same chamber and by using the same sputtering target as the signal line, or a buffer layer of an oxide layer including aluminum is formed in a contact hole exposing the signal line during the formation of the contact hole. Accordingly, the contact characteristic between an upper layer including indium tin oxide (“ITO”) or indium zinc oxide (“IZO”) and the signal line may be improved to enhance the adhesion therebetween while not increasing the production cost of the thin film transistor (“TFT”) array panel.

摘要翻译： 在形成包括铝的信号线之后，在相同的室中形成包含覆盖信号线的铝的氧化物层的上层，并且通过使用与信号线相同的溅射靶，或者包括铝的氧化物层的缓冲层 形成在接触孔形成期间暴露信号线的接触孔中。 因此，可以改善包括氧化铟锡（“ITO”）或氧化铟锌（“IZO”）的上层与信号线之间的接触特性，以增强其之间的粘附，同时不增加薄膜晶体管的生产成本 （“TFT”）阵列面板。

公开(公告)号：US20090224257A1

公开(公告)日：2009-09-10

申请号：US12390076

申请日：2009-02-20

申请人： Hong-Kee CHIN ,  Shin-Il CHOI ,  Sang-Gab KIM ,  Min-Seok OH ,  Yu-Gwang JEONG ,  Seung-Ha CHOI ,  Dong-Ju YANG

发明人： Hong-Kee CHIN ,  Shin-Il CHOI ,  Sang-Gab KIM ,  Min-Seok OH ,  Yu-Gwang JEONG ,  Seung-Ha CHOI ,  Dong-Ju YANG

IPC分类号： H01L33/00

CPC分类号： H01L29/458 ,  H01L27/124

摘要： A thin film transistor array panel includes a gate line formed on a substrate and including a gate electrode, a semiconductor layer formed on a surface of the substrate having the gate line, a data line formed on the semiconductor layer, insulatedly intersecting the gate line, and including a source electrode disposed on the gate electrode, a drain electrode separated from the source electrode by a channel, disposed on the gate electrode, and formed from the same layer as the data line, a passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode, and a pixel electrode formed on the passivation layer and contacting the drain electrode through the first contact hole. The data line and the drain electrode may include a first layer and a second layer formed on the first layer, a planar edge of the first layer protrudes from a planar edge of the second layer, and the first layer is formed by dry-etching and the second layer is formed by wet-etching.

摘要翻译： 薄膜晶体管阵列面板包括形成在基板上并包括栅电极的栅极线，形成在具有栅极线的基板的表面上的半导体层，形成在半导体层上的与栅极线绝缘相交的数据线， 并且包括设置在栅电极上的源电极，通过沟道与源电极分离的漏极，设置在栅电极上，并由与数据线相同的层形成，形成在数据线上的钝化层和 漏极，并且具有暴露漏电极的第一接触孔，以及形成在钝化层上并通过第一接触孔接触漏电极的像素电极。 数据线和漏极可以包括形成在第一层上的第一层和第二层，第一层的平面边缘从第二层的平坦边缘突出，并且第一层通过干蚀刻形成， 第二层通过湿法蚀刻形成。

公开(公告)号：US20090206343A1

公开(公告)日：2009-08-20

申请号：US12372212

申请日：2009-02-17

申请人： Seung-Ha CHOI ,  Min-Seok OH ,  Sang-Gab KIM ,  Hong-Kee CHIN ,  Yu-Gwang JEONG

发明人： Seung-Ha CHOI ,  Min-Seok OH ,  Sang-Gab KIM ,  Hong-Kee CHIN ,  Yu-Gwang JEONG

IPC分类号： H01L33/00

CPC分类号： H01L27/124 ,  G02F1/136286 ,  G02F2001/136222 ,  G02F2001/136295 ,  H01L27/1248 ,  H01L27/1288

摘要： In a display apparatus and a method of manufacturing the display apparatus, a first insulating layer having a trench and a second insulating layer having a via hole corresponding to the trench are formed on an array substrate. After forming a seed layer in the trench, a conductive layer is formed on the seed layer through a plating process, thereby forming the gate line, the gate electrode and the storage line accommodated in the trench and the via hole.

摘要翻译： 在显示装置和显示装置的制造方法中，在阵列基板上形成具有沟槽的第一绝缘层和具有与沟槽对应的通路孔的第二绝缘层。 在沟槽中形成晶种层之后，通过电镀工艺在晶种层上形成导电层，从而形成栅极线，栅极电极和容纳在沟槽和通孔中的存储线。

公开(公告)号：US20110297931A1

公开(公告)日：2011-12-08

申请号：US13210282

申请日：2011-08-15

申请人： Dong-Ju YANG ,  Yu-Gwang JEONG ,  Ki-Yeup LEE ,  Sang-Gab KIM ,  Yun-Jong YEO ,  Shin-Il CHOI ,  Hong-Kee CHIN ,  Seung-Ha CHOI ,  Jung-Suk BANG

发明人： Dong-Ju YANG ,  Yu-Gwang JEONG ,  Ki-Yeup LEE ,  Sang-Gab KIM ,  Yun-Jong YEO ,  Shin-Il CHOI ,  Hong-Kee CHIN ,  Seung-Ha CHOI ,  Jung-Suk BANG

IPC分类号： H01L29/786

CPC分类号： H01L27/1248 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/7869

摘要： A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.

摘要翻译： 提出了制造薄膜晶体管阵列基板的方法。 该方法需要在绝缘基板上形成栅极互连线，在栅极互连线上形成栅极绝缘层，在半导体层上形成半导体层和数据互连线，依次形成多个钝化层，将钝化层蚀刻到 作为数据互连线的延伸线的漏电极。 在该阶段暴露的漏电极的部分是漏极电极 - 像素电极接触部分的一部分。 形成连接到漏电极的像素电极。 两个钝化层具有相同的组成，但是在不同的温度下进行处理。 还提出了以上述方式制备的薄膜晶体管。

公开(公告)号：US20080280379A1

公开(公告)日：2008-11-13

申请号：US11933413

申请日：2007-10-31

申请人： Min-Seok OH ,  Sang-Gab KIM ,  Hong-Kee CHIN ,  Yu-Gwang JEONG ,  Seung-Ha CHOI ,  Ki-Hyun KIM ,  In-Ho SONG

发明人： Min-Seok OH ,  Sang-Gab KIM ,  Hong-Kee CHIN ,  Yu-Gwang JEONG ,  Seung-Ha CHOI ,  Ki-Hyun KIM ,  In-Ho SONG

IPC分类号： H01L21/66 ,  H01L21/67

CPC分类号： H01L22/12 ,  H01L27/1288 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a method of manufacturing a thin film transistor substrate and a manufacturing system using the same, wherein the production of corrosive substances is reduced during the process of manufacturing the thin film transistor substrate. The method includes providing an etching unit with an insulation substrate on which a thin metal film has been deposited, and dry-etching the insulation substrate so as to form a predetermined circuit pattern; providing a waiting unit with the insulation substrate waiting to be cleaned; performing a preliminary cleaning operation by a cleaning unit having a plurality of nozzles while the insulation substrate waits and checking the preliminary cleaning operation; and performing a main cleaning operation with regard to the insulation substrate based on the result of the check.

摘要翻译： 提供一种制造薄膜晶体管基板的方法和使用该薄膜晶体管基板的制造系统，其中在制造薄膜晶体管基板的过程中，腐蚀性物质的产生减少。 该方法包括：提供具有绝缘基板的蚀刻单元，在其上沉积有薄金属膜，并对绝缘基板进行干蚀刻以形成预定的电路图案; 提供等待单元与等待清理的绝缘基板; 在绝缘基板等待并检查预备清洗操作的同时，通过具有多个喷嘴的清洗单元执行初步清洁操作; 并且基于检查结果对绝缘基板进行主清洗操作。

公开(公告)号：US20080145980A1

公开(公告)日：2008-06-19

申请号：US12030992

申请日：2008-02-14

申请人： Bo Sung KIM ,  Kwan-Wook JUNG ,  Wan-Shick HONG ,  Sang-Gab KIM ,  Mun-Pyo HONG

发明人： Bo Sung KIM ,  Kwan-Wook JUNG ,  Wan-Shick HONG ,  Sang-Gab KIM ,  Mun-Pyo HONG

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： G02F1/13458 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1248 ,  H01L27/1288

摘要： A method for manufacturing a semiconductor device including forming a first wire on a substrate, forming a lower film on the first wire, forming a photosensitive pattern on the lower film using a photosensitive material, forming contact holes for exposing the first wire by etching the lower film using the photosensitive film as an etching mas, removing part of the photosensitive film pattern by an ashing process to expose a borderline of the lower film defining the contact holes and forming second wire connected to the firs wire via the contact holes.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成第一线，在第一线上形成下膜，使用感光材料在下膜上形成感光图案，形成用于通过蚀刻下部的第一线露出的接触孔 使用感光膜作为蚀刻的膜，通过灰化处理去除部分感光膜图案以暴露限定接触孔的下膜的边界，并且形成通过接触孔连接到第一线的第二线。

公开(公告)号：US20100148182A1

公开(公告)日：2010-06-17

申请号：US12429388

申请日：2009-04-24

申请人： Hong-Kee CHIN ,  Sang-Gab KIM ,  Woong-Kwon KIM ,  Yong-Mo CHOI ,  Seung-Ha CHOI ,  Shin-Il CHOI ,  Ho-Jun LEE ,  Jung-Suk BANG ,  Yu-Gwang JEONG

发明人： Hong-Kee CHIN ,  Sang-Gab KIM ,  Woong-Kwon KIM ,  Yong-Mo CHOI ,  Seung-Ha CHOI ,  Shin-Il CHOI ,  Ho-Jun LEE ,  Jung-Suk BANG ,  Yu-Gwang JEONG

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/12 ,  H01L27/1248 ,  H01L27/1288

摘要： A thin film transistor (TFT) substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion and a method of fabricating the TFT substrate. The TFT substrate includes a gate interconnection line formed on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode and a drain electrode formed on the semiconductor layer, a first passivation layer formed on the data interconnection line and exposing the drain electrode, a second passivation layer formed on the first passivation film and a pixel electrode electrically connected to the drain electrode. An outer sidewall of the second passivation layer is positioned inside an outer sidewall of the first passivation layer.

摘要翻译： 提供一种薄膜晶体管（TFT）基板，其中在接触部分中提供导电材料之间的足够大的接触面积以及制造TFT基板的方法。 TFT基板包括形成在绝缘基板上的栅极互连线，覆盖栅极互连线的栅极绝缘层，布置在栅极绝缘层上的半导体层，包括数据线，源极和漏极的数据互连线 形成在所述半导体层上，形成在所述数据互连线上并暴露所述漏电极的第一钝化层，形成在所述第一钝化膜上的第二钝化层和与所述漏电极电连接的像素电极。 第二钝化层的外侧壁位于第一钝化层的外侧壁的内侧。