利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

72 条记录 (耗时 0.03 秒)

    Multi-layer chip capacitor
    1.
    发明申请
    Multi-layer chip capacitor 失效
    多层片式电容器

    公开(公告)号：US20060120018A1

    公开(公告)日：2006-06-08

    申请号：US11272877

    申请日：2005-11-15

    申请人： Byoung Lee ,  Chang Shim ,  Kyong Hwang ,  Dong Park ,  Sang Park ,  Min Park

    发明人： Byoung Lee ,  Chang Shim ,  Kyong Hwang ,  Dong Park ,  Sang Park ,  Min Park

    IPC分类号： H01G4/228

    CPC分类号： H01G4/232 ,  H01G4/30

    摘要： A multi-layer chip capacitor comprises a capacitor body formed by stacking a plurality of dielectric layers; a plurality of first and second internal electrodes formed on the dielectric layers, each having at least one through hole formed through at least one side thereof; lowermost electrode patterns, each including a lead portion extended to one side of the capacitor body, and a via contact portion; a plurality of conductive vias, vertically extended to pass through the through holes so as not to contact the inner surfaces of the through holes, each of the contact vias connected to either the first or second internal electrode and contacting the via contact portion; and a plurality of terminal electrodes formed on the outer surface of the capacitor body, and connected to the conductive vias through the lead portions. The conductive vias connected to the first internal electrodes are connected to the terminal electrodes having a first polarity, and the conductive vias connected to the second internal electrodes are connected to the terminal electrodes having a second polarity.

    摘要翻译： 多层片状电容器包括通过层叠多个电介质层而形成的电容器本体; 形成在所述电介质层上的多个第一和第二内部电极，每个所述第一和第二内部电极具有通过至少一个侧面形成的至少一个通孔; 每个包括延伸到电容器主体的一侧的引线部分和通孔接触部分的最下面的电极图案; 多个导电通孔，垂直延伸以穿过通孔，以便不与通孔的内表面接触;每个接触通孔连接到第一或第二内部电极，并接触通孔接触部分; 以及多个端子电极，形成在电容器主体的外表面上，并且通过引线部分连接到导电通孔。 连接到第一内部电极的导电通孔连接到具有第一极性的端子电极，并且连接到第二内部电极的导电通孔连接到具有第二极性的端子电极。

    Multilayer chip capacitor
    2.
    发明申请
    Multilayer chip capacitor 失效
    多层片式电容器

    公开(公告)号：US20060285271A1

    公开(公告)日：2006-12-21

    申请号：US11453880

    申请日：2006-06-16

    申请人： Byoung Lee ,  Chang Shim ,  Hae Chung ,  Dong Park ,  Sang Park ,  Min Park

    发明人： Byoung Lee ,  Chang Shim ,  Hae Chung ,  Dong Park ,  Sang Park ,  Min Park

    IPC分类号： H01G4/005

    CPC分类号： H01G4/30 ,  H01G4/232

    摘要： The invention provides a multilayer chip capacitor reduced in ESL. A capacitor body has a plurality of dielectric layers stacked in a thickness direction. A plurality of first and second internal electrodes are separated from one another by the dielectric layers within the capacitor body. Each of the first internal electrodes opposes each of the second internal electrodes. Each of the first and second internal electrodes includes at least two leads extending toward any side of the capacitor body. Also, a plurality of external electrodes are formed on an outer surface of the capacitor body and connected to the internal electrodes via the leads. Further, vertically adjacent ones of the leads having the same polarity extend in different directions at a predetermined angle. The leads of the first and second internal electrodes are disposed adjacent to and alternate with those of the second internal electrodes.

    摘要翻译： 本发明提供了一种减少ESL的多层片式电容器。 电容器本体具有沿厚度方向堆叠的多个电介质层。 多个第一和第二内部电极通过电容器主体内的电介质层彼此分离。 每个第一内部电极与每个第二内部电极相对。 第一和第二内部电极中的每一个包括朝向电容器主体的任何一侧延伸的至少两个引线。 此外，多个外部电极形成在电容器主体的外表面上并通过引线连接到内部电极。 此外，具有相同极性的垂直相邻的引线以预定角度在不同方向上延伸。 第一和第二内部电极的引线设置成与第二内部电极的引线相邻并与其交替。

    MULTILAYER CHIP CAPACITOR
    3.
    发明申请
    MULTILAYER CHIP CAPACITOR 有权
    多层芯片电容器

    公开(公告)号：US20060158827A1

    公开(公告)日：2006-07-20

    申请号：US11068825

    申请日：2005-03-02

    申请人： Byoung Lee ,  Chang Shim ,  Hae Chung ,  Dong Park ,  Sang Park ,  Min Park

    发明人： Byoung Lee ,  Chang Shim ,  Hae Chung ,  Dong Park ,  Sang Park ,  Min Park

    IPC分类号： H01G4/06

    CPC分类号： H01G4/30 ,  H01G4/232

    摘要： A multilayer chip capacitor, which reduces ESL generated due to current flowing through external electrodes and assures an improved mechanical strength. The multilayer chip capacitor includes an upper dummy layer and a lower dummy layer; a plurality of internal electrodes interposed between the upper and lower dummy layers; and external electrodes connected to the internal electrodes, wherein the thickness of the lower dummy layer is smaller than the thickness of the upper dummy layer.

    摘要翻译： 一种多层片状电容器，其减少由于电流流过外部电极而产生的ESL，并确保改进的机械强度。 多层片状电容器包括上虚拟层和下虚拟层; 插入在上下虚拟层之间的多个内部电极; 以及连接到内部电极的外部电极，其中下部虚拟层的厚度小于上部虚拟层的厚度。

    Laminated ceramic capacitor
    5.
    发明申请
    Laminated ceramic capacitor 有权

    公开(公告)号：US20060018081A1

    公开(公告)日：2006-01-26

    申请号：US11068757

    申请日：2005-03-02

    申请人： Byoung Hwa Lee ,  Dong Park ,  Min Park ,  Sang Park ,  Chang Shim ,  Kyung Hwang

    发明人： Byoung Hwa Lee ,  Dong Park ,  Min Park ,  Sang Park ,  Chang Shim ,  Kyung Hwang

    IPC分类号： H01G4/06

    CPC分类号： H01G4/012 ,  H01G4/30

    摘要： A laminated ceramic capacitor includes a ceramic block formed by laminating a plurality of ceramic sheets, a plurality of external electrodes formed on outer surfaces of the ceramic block facing each other, and set as a positive terminal and a negative terminal, respectively, one or more first and second internal electrodes alternately arranged within the ceramic block such that electric currents flow in opposite directions in the internal electrodes, and a plurality of withdrawing patterns for connecting the first and second internal electrodes to the external electrodes, respectively.

    Multilayer chip capacitor
    6.
    发明申请
    Multilayer chip capacitor 有权
    多层片式电容器

    公开(公告)号：US20070109717A1

    公开(公告)日：2007-05-17

    申请号：US11598672

    申请日：2006-11-14

    申请人： Byoung Lee ,  Hae Chung ,  Dong Park ,  Min Park ,  Sang Park ,  Sung Wi

    发明人： Byoung Lee ,  Hae Chung ,  Dong Park ,  Min Park ,  Sang Park ,  Sung Wi

    IPC分类号： H01G4/005

    CPC分类号： H01G4/30 ,  H01G4/012 ,  H01G4/232

    摘要： A multilayer chip capacitor includes a capacitor body having dielectric layers, and internal electrode layers separated from each other in the capacitor body by the dielectric layers. Each internal electrode layer has one or two leads and includes at least one coplanar electrode plate. External electrodes are electrically connected to the internal electrode layers via the leads. The internal electrode layers constitute a plurality of blocks stacked repeatedly. Each block includes a plurality of the internal electrode layers stacked successively. The leads extending to a face of the capacitor body are arranged in a zigzag shape along a stacking direction. The leads of vertically adjacent ones of the electrode plates having opposite polarities are arranged to be horizontally adjacent to each other.

    摘要翻译： 多层片状电容器包括具有电介质层的电容器主体，以及通过电介质层在电容器主体中彼此分离的内部电极层。 每个内部电极层具有一个或两个引线并且包括至少一个共面电极板。 外部电极通过引线电连接到内部电极层。 内部电极层构成反复堆叠的多个块。 每个块包括依次层叠的多个内部电极层。 延伸到电容器主体的表面的引线沿堆叠方向布置成Z字形。 具有相反极性的垂直相邻电极板的引线被布置成水平相邻。

    Laminated balun transformer
    7.
    发明申请
    Laminated balun transformer 有权
    叠层平衡不平衡变压器

    公开(公告)号：US20060061430A1

    公开(公告)日：2006-03-23

    申请号：US11067872

    申请日：2005-02-28

    申请人： Byoung Lee ,  Dong Park ,  Min Park ,  Sang Park

    发明人： Byoung Lee ,  Dong Park ,  Min Park ,  Sang Park

    IPC分类号： H01P5/10

    CPC分类号： H01P5/10

    摘要： The present invention relates a laminated balun transformer with an improved insertion loss characteristic in a pass band. The laminated balun transformer includes a first strip line and a third strip line form one coupler, a second strip line and a fourth strip line form another coupler, and a conductive non-ground electrode formed at an intermediate position between the third strip line and the fourth strip line. The non-ground electrode forms a ground by electromagnetic coupling between the third strip line and the fourth strip line. With the configuration, insertion loss in an operation band is reduced. In addition, by implementing an impedance and an electromagnetic shield using a ground pattern of a mount surface without separately forming an internal ground electrode on the bottom layer of a dielectric block, of ground electrodes formed above and below the first to fourth strip lines for the electromagnetic shield from the outside, the thickness of the laminated balun transformer can be reduced without any deterioration of characteristic of the transformer.

    摘要翻译： 本发明涉及在通带中具有改进的插入损耗特性的层叠平衡不平衡变压器。 所述叠层平衡不平衡转换器包括形成一个耦合器的第一带状线和第三带状线，形成另一个耦合器的第二带状线和第四带状线，以及形成在第三带状线和第三带状线之间的中间位置的导电非接地电极 第四条线。 非接地电极通过第三带状线和第四带状线之间的电磁耦合形成接地。 通过该结构，能够减少操作频带的插入损失。 此外，通过使用安装面的接地图案来实现阻抗和电磁屏蔽，而不在介质块的底层上分开形成内部接地电极，形成在第一至第四条带状线之上和之下的接地电极，用于 电磁屏蔽从外部，层压平衡不平衡变压器的厚度可以减小，而不会导致变压器特性的恶化。

    Laminated balun transformer
    8.
    发明申请
    Laminated balun transformer 有权
    叠层平衡不平衡变压器

    公开(公告)号：US20060061429A1

    公开(公告)日：2006-03-23

    申请号：US11065232

    申请日：2005-02-24

    申请人： Byoung Lee ,  Dong Park ,  Min Park ,  Sang Park

    发明人： Byoung Lee ,  Dong Park ,  Min Park ,  Sang Park

    IPC分类号： H03H5/10

    CPC分类号： H01P5/10

    摘要： A laminated balun transformer subminiaturized with a transmission line length reduced below λ/4 without any variation of characteristics. The laminated balun transformer includes a first strip line having one end inputted to a unbalanced signal; a second strip line having connected to the first strip line; a third strip line formed in parallel with the first strip line and connected to a ground and connected to the external electrode for a first balanced signal; a fourth strip line formed in parallel with the second strip line and connected to the external electrode for a ground and the external electrode for a second balanced signal; and a capacitance forming electrode formed in parallel with a portion of the opened end of the second strip line and connected to the external electrode for the unbalanced signal.

    摘要翻译： 传输线长度小于λ/ 4的小型化的不平衡 - 不平衡转换变压器，没有任何特性变化。 叠层平衡不平衡变压器包括：一端输入不平衡信号的第一带状线; 连接到第一带状线的第二带状线; 第三带状线，与第一带状线平行地形成并连接到接地并连接到外部电极用于第一平衡信号; 第四带状线，与第二条带线平行地形成并连接到用于接地的外部电极和用于第二平衡信号的外部电极; 以及电容形成电极，其与所述第二带状线的开放端部的一部分平行地形成，并且与所述不平衡信号的外部电极连接。

    Laminated low pass filter
    9.
    发明申请
    Laminated low pass filter 审中-公开
    层压低通滤波器

    公开(公告)号：US20050077984A1

    公开(公告)日：2005-04-14

    申请号：US10735616

    申请日：2003-12-16

    申请人： Byoung Lee ,  Jeong Yoon ,  Yong Park ,  Dong Park ,  Sang Park ,  Min Park

    发明人： Byoung Lee ,  Jeong Yoon ,  Yong Park ,  Dong Park ,  Sang Park ,  Min Park

    IPC分类号： H03H7/075 ,  H01P1/203

    CPC分类号： H01P1/2039

    摘要： A laminated low pass filter including a dielectric block having a plurality of laminated dielectric layers, input and output electrodes and outer ground electrodes formed on outer side surfaces of the dielectric block, so as to pass therethrough a signal inputted to the outer input electrode, only in a low frequency band, and then to output the passed signal to the outer output electrode. The laminated low pass filter also includes a transmission line including a distributed constant element made of a strip line formed on a first one of the dielectric layers, while being uniformly distributed with an inductance and a capacitance, the distributed constant element being connected between the input electrode and the output electrode, and a capacitor electrode structure having at least two layers while being connected between the input electrode and the output electrode. The capacitance electrode structure forms a capacitance connected in parallel to the transmission line. Since the laminated low pass filter is simply implemented by use of the transmission line and capacitors formed on the dielectric block having a multilayer structure, it can have a miniature size while exhibiting improved insertion loss characteristics, as compared to conventional laminated low pass filters implemented by use of concentrated constant elements.

    摘要翻译： 一种层叠低通滤波器，包括具有多个叠层电介质层的介质块，形成在介质块的外侧表面上的输入和输出电极和外部接地电极，以便仅通过输入到外部输入电极的信号 在低频带中，然后将通过的信号输出到外部输出电极。 层叠低通滤波器还包括传输线，其包括由形成在第一介质层上的带状线制成的分布常数元件，同时以电感和电容均匀分布，分布常数元件连接在输入 电极和输出电极，以及具有至少两层的电容器电极结构，同时连接在输入电极和输出电极之间。 电容电极结构形成与传输线并联连接的电容。 由于层叠低通滤波器简单地通过使用传输线和形成在具有多层结构的介质块上的电容器来实现，与传统的层叠低通滤波器相比，它可以具有小尺寸，同时具有改进的插入损耗特性， 使用集中的常数元素。