公开(公告)号：US20060092595A1

公开(公告)日：2006-05-04

申请号：US11264486

申请日：2005-11-01

申请人： Byoung Hwa Lee ,  Hiroki Sato ,  Chang Shim ,  Sang Park ,  Hae Chung ,  Dong Park ,  Min Park ,  Hyun Yi ,  Min Kwon ,  Seung Han

发明人： Byoung Hwa Lee ,  Hiroki Sato ,  Chang Shim ,  Sang Park ,  Hae Chung ,  Dong Park ,  Min Park ,  Hyun Yi ,  Min Kwon ,  Seung Han

IPC分类号： H01G4/228

CPC分类号： H05K1/0231 ,  H01G2/065 ,  H01G4/228 ,  H01G4/30 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/15159 ,  H01L2924/19041 ,  H01L2924/19106 ,  H05K2201/10515 ,  H05K2201/1053 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Disclosed herein is a multilayered chip capacitor array, including a capacitor body having a plurality of dielectric layers, a plurality of pairs of first and second inner electrodes which are formed on the plurality of dielectric layers such that one electrode of one pair of inner electrodes faces the other electrode of the one pair of inner electrodes with one of the plurality of dielectric layers interposed therebetween, at least one first outer terminal and a plurality of second outer terminals formed on at least one surface of a top surface and a bottom surface of the capacitor body, and at least one first conductive via and a plurality of second conductive vias formed in a stacking direction of the capacitor body and connected to the first outer terminal and the second outer terminal, respectively.

公开(公告)号：US20060082854A1

公开(公告)日：2006-04-20

申请号：US11244562

申请日：2005-10-06

申请人： Yoon Hong ,  Seung An ,  Seung Han ,  Hyun Yi

发明人： Yoon Hong ,  Seung An ,  Seung Han ,  Hyun Yi

IPC分类号： G02B26/00

CPC分类号： G02B26/0808

摘要： Disclosed is a fishbone diffraction-type light modulator. In the fishbone diffraction-type light modulator, a lower micromirror is provided on a silicone substrate, and an upper micromirror is spaced apart from the silicone substrate and has a plurality of openings through both sides thereof. The upper micromirror and the lower micromirror deposited on the silicone substrate form pixels.

摘要翻译： 披露的是鱼骨衍射型光调制器。 在鱼骨衍射型光调制器中，在硅树脂基底上设置下微反射镜，并且上微镜与硅树脂基底间隔开，并且在其两侧具有多个开口。 沉积在硅树脂衬底上的上微镜和下微镜形成像素。

公开(公告)号：US20060146392A1

公开(公告)日：2006-07-06

申请号：US11244605

申请日：2005-10-06

申请人： Seung An ,  Yoon Hong ,  Seung Han ,  Hyun Yi

发明人： Seung An ,  Yoon Hong ,  Seung Han ,  Hyun Yi

IPC分类号： G02B26/00

CPC分类号： G02B26/0808

摘要： Disclosed herein is an interdigitation-type diffractive light modulator. In the interdigitation-type diffractive light modulator of the present invention, each of a pair of ribbons has a plurality of diffractive branches which are arranged in a comb shape, and the diffractive branches of the ribbons interdigitate with each other. Furthermore, the respective ribbons moves upwards and downwards or, alternatively, one ribbon moves upwards and downwards, so that the diffractive branches of the ribbons which interdigitate with each other form a stepped structure, thus diffracting incident light.

摘要翻译： 这里公开了一种交叉指型衍射光调制器。 在本发明的交叉指型衍射光调制器中，一对带具有多个衍生分支，其梳状布置，并且色带的衍射分支彼此相互指向。 此外，相应的带子向上和向下移动，或者替代地，一个带状物向上和向下移动，使得相互交错的条带的衍射分支形成阶梯状结构，从而衍射入射光。

公开(公告)号：US20070157058A1

公开(公告)日：2007-07-05

申请号：US11616471

申请日：2006-12-27

申请人： Chang Park ,  Ki Jeon ,  Young Kim ,  Jae Son ,  Hyun Yi ,  Sung Park

发明人： Chang Park ,  Ki Jeon ,  Young Kim ,  Jae Son ,  Hyun Yi ,  Sung Park

IPC分类号： G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/31855

摘要： An interconnect delay fault test controller and a test apparatus using the same wherein an update operation and a capture operation may be carried out in one interval of a system clock or a core clock when carrying out an interconnect delay fault test between an IEEE P1500 wrapped cores in a SoC as well as an interconnect wire on a board based on an IEEE 1149.1, and wherein the interconnect delay fault test using different system clocks or core clocks may be carried out simultaneously in one test cycle corresponding to each system clock or core clock even when multiple system clocks or core clocks exists is disclosed.

摘要翻译： 一种互连延迟故障测试控制器和使用该互连延迟故障测试控制器的测试装置，其中当在IEEE P1500封装核心之间执行互连延迟故障测试时，可以在系统时钟或核心时钟的一个间隔中执行更新操作和捕获操作 在SoC以及基于IEEE 1149.1的板上的互连线，并且其中使用不同系统时钟或核心时钟的互连延迟故障测试可以在对应于每个系统时钟或核心时钟的一个测试周期中同时执行，甚至 当公开了多个系统时钟或核心时钟时。

公开(公告)号：US20070059877A1

公开(公告)日：2007-03-15

申请号：US11305500

申请日：2005-12-15

申请人： Hyun Koo ,  Suk Han ,  Jong Eom ,  Joon Chang ,  Hyun Yi

发明人： Hyun Koo ,  Suk Han ,  Jong Eom ,  Joon Chang ,  Hyun Yi

IPC分类号： H01L21/8238

CPC分类号： H01L29/66984 ,  H01F1/404 ,  H01F10/193 ,  H01L29/0843 ,  H01L29/772

摘要： A spin transistor having wide ON/OFF operation margin and producing less noise is provided. The spin transistor includes a substrate having a channel, a source, a drain and a gate formed on the substrate. The source and the drain are formed to have magnetization directions perpendicular to the length direction of the channel. The ON/OFF operations of the spin transistor can be controlled by generating a spin-orbit coupling induced magnetic field to have a direction parallel or anti-parallel to the magnetization directions of the source and the drain.

摘要翻译： 提供具有宽的ON / OFF操作余量并产生较少噪声的自旋晶体管。 自旋晶体管包括具有在衬底上形成的沟道，源极，漏极和栅极的衬底。 源极和漏极形成为具有与沟道的长度方向垂直的磁化方向。 可以通过产生自旋轨道耦合感应磁场来使源极和漏极的磁化方向平行或反平行的方向来控制自旋晶体管的ON / OFF操作。

公开(公告)号：US08004308B2

公开(公告)日：2011-08-23

申请号：US12780917

申请日：2010-05-16

申请人： Vikram Santurkar ,  Hyun Yi

发明人： Vikram Santurkar ,  Hyun Yi

IPC分类号： H03K17/16

CPC分类号： H03K19/0005 ,  H04L25/0278 ,  H04L25/0298

摘要： Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.

摘要翻译： 提供了用于校准集成电路上的片上终端阻抗的技术。 片上终止（OCT）校准电路产生校准代码，其选择性地控制并联耦合的一组晶体管的导通状态。 OCT校准电路选择使晶体管的阻抗接近匹配阻抗的校准码。 所选的校准代码控制引脚上的片上终端阻抗。 根据一些实施例，OCT校准电路将来自晶体管的信号与两个或更多个参考信号进行比较，以改进校准的片上终端阻抗的容差范围。 根据其他实施例，OCT校准电路在通过控制信号接通附加晶体管之后，基于来自晶体管的信号来选择校准码。 控制信号不用于控制片上终端阻抗。

公开(公告)号：US07855574B2

公开(公告)日：2010-12-21

申请号：US11548206

申请日：2006-10-10

申请人： Vikram Santurkar ,  Ravi Thiruveedhula ,  Hyun Yi

发明人： Vikram Santurkar ,  Ravi Thiruveedhula ,  Hyun Yi

IPC分类号： H03K19/094

CPC分类号： H03K19/018521 ,  H03K19/094

摘要： A level conversion architecture that accommodates signals traveling between logic blocks operating at corresponding voltage levels is provided. The architecture includes pass gates connected in series between the logic blocks. One of the gates of the pass gates is supplied with a selectable gate voltage supply. The selectable gate voltage supply is selected from a plurality of voltages based on a configuration random access memory (CRAM) setting. In one embodiment, a half latch is connected to one of the pass gates. In this embodiment, the half latch is part of a feedback loop to minimize power leakage of a logic element in one of the logic blocks. A method for managing power consumption and providing voltage level conversion between regions of an integrated circuit is also provided.

摘要翻译： 提供了一种电平转换架构，其适应在以相应电压电平工作的逻辑块之间行进的信号。 该架构包括在逻辑块之间串联连接的通道。 通过门的一个门提供可选择的栅极电压源。 基于配置随机存取存储器（CRAM）设置从多个电压中选择可选择的栅极电压源。 在一个实施例中，半锁存器连接到一个通过门。 在该实施例中，半锁存器是反馈回路的一部分，以最小化逻辑块之一中的逻辑元件的功率泄漏。 还提供了一种用于管理功率消耗并在集成电路的区域之间提供电压电平转换的方法。

公开(公告)号：US20080061818A1

公开(公告)日：2008-03-13

申请号：US11466451

申请日：2006-08-22

申请人： Vikram Santurkar ,  Hyun Yi

发明人： Vikram Santurkar ,  Hyun Yi

IPC分类号： H03K19/003

CPC分类号： H03K19/0005 ,  H04L25/0278 ,  H04L25/0298

摘要： Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.

摘要翻译： 提供了用于校准集成电路上的片上终端阻抗的技术。 片上终止（OCT）校准电路产生校准代码，其选择性地控制并联耦合的一组晶体管的导通状态。 OCT校准电路选择使晶体管的阻抗接近匹配阻抗的校准码。 所选的校准代码控制引脚上的片上终端阻抗。 根据一些实施例，OCT校准电路将来自晶体管的信号与两个或更多个参考信号进行比较，以改进校准的片上终端阻抗的容差范围。 根据其他实施例，OCT校准电路在通过控制信号接通附加晶体管之后，基于来自晶体管的信号来选择校准码。 控制信号不用于控制片上终端阻抗。

公开(公告)号：US07884638B1

公开(公告)日：2011-02-08

申请号：US12236201

申请日：2008-09-23

申请人： Vikram Santurkar ,  Hyun Yi

发明人： Vikram Santurkar ,  Hyun Yi

IPC分类号： H03K17/16

CPC分类号： H03K17/005 ,  H03H11/28 ,  H03K17/16 ,  H03K17/165 ,  H03K17/6872 ,  H04L25/0278 ,  H04L25/0298

摘要： An on-chip termination (OCT) calibration circuit includes one or more transistors coupled between a first terminal and a supply voltage, one or more transistors coupled between the first terminal and a low voltage, and a feedback loop circuit. The feedback loop circuit compares a signal from the first terminal to first and second reference signals to generate a first calibration code that controls conductive states of the one or more transistors coupled between the first terminal and the supply voltage and a second calibration code that controls conductive states of the one or more transistors coupled between the first terminal and the low voltage. The OCT calibration circuit controls an on-chip termination impedance at a pin using the first calibration code and the second calibration code.

摘要翻译： 片上终端（OCT）校准电路包括耦合在第一端子和电源电压之间的一个或多个晶体管，耦合在第一端子和低电压之间的一个或多个晶体管，以及反馈环路电路。 反馈回路电路将来自第一端子的信号与第一和第二参考信号进行比较，以产生控制耦合在第一端子和电源电压之间的一个或多个晶体管的导通状态的第一校准代码，以及控制导电 耦合在第一端子和低电压之间的一个或多个晶体管的状态。 OCT校准电路使用第一个校准代码和第二个校准代码控制引脚上的片上终端阻抗。

公开(公告)号：US20100228806A1

公开(公告)日：2010-09-09

申请号：US12716878

申请日：2010-03-03

申请人： Keone Streicher ,  Martin Langhammer ,  Yi-Wen Lin ,  Wai-Bor Leung ,  David Lewis ,  Volker Mauer ,  Henry Y. Lul ,  Suleyman Sirri Demirsoy ,  Hyun Yi

发明人： Keone Streicher ,  Martin Langhammer ,  Yi-Wen Lin ,  Wai-Bor Leung ,  David Lewis ,  Volker Mauer ,  Henry Y. Lul ,  Suleyman Sirri Demirsoy ,  Hyun Yi

IPC分类号： G06F7/52 ,  G06F5/01 ,  G06F7/00

CPC分类号： G06F17/10 ,  G06F7/5324 ,  G06F2207/382 ,  H03H17/06 ,  H03H2220/06 ,  H03K19/17732

摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

摘要翻译： 提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。 尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。 收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。