公开(公告)号：US06699625B2

公开(公告)日：2004-03-02

申请号：US09976566

申请日：2001-10-12

申请人： Byoung-taek Lee ,  Taro Ogawa ,  Biichi Hoshino

发明人： Byoung-taek Lee ,  Taro Ogawa ,  Biichi Hoshino

IPC分类号： G03F900

CPC分类号： G03F1/24 ,  G03F1/38

摘要： Reflection photomasks add a buffer layer including at least one Group VIII metal between a reflection layer and an absorber pattern that is configured to absorb extreme ultraviolet rays therein. In particular, reflection photomasks include a substrate and a reflection layer having multiple sets of alternating films of first and second materials, on the substrate. A buffer layer including at least one Group VIII metal is provided on the reflection layer opposite the substrate. An absorber pattern including material that is patterned in a pattern and that is configured to absorb extreme ultraviolet rays, is provided on the buffer layer opposite the reflection layer. The at least one Group VIII metal preferably is Ru. At least a portion of the Ru buffer layer may be less than about 3 nm thick. Alternatively, the Group VIII metal can include Pt, Ir and/or Pd.

摘要翻译： 反射光掩模在反射层和吸收体图案之间添加包括至少一个VIII族金属的缓冲层，该反射层和吸收体图案被配置为吸收其中的极紫外线。 特别地，反射光掩模包括基板和在基板上具有多组第一和第二材料的交替膜的反射层。 在与衬底相对的反射层上设置包括至少一种第VIII族金属的缓冲层。 在与反射层相反的缓冲层上设置有包括以图案图案化并且被配置为吸收极紫外线的材料的吸收体图案。 至少一种VIII族金属优选为Ru。 Ru缓冲层的至少一部分可以小于约3nm厚。 或者，VIII族金属可以包括Pt，Ir和/或Pd。

公开(公告)号：US5780115A

公开(公告)日：1998-07-14

申请号：US806145

申请日：1997-02-25

申请人： In-sung Park ,  Byoung-taek Lee

发明人： In-sung Park ,  Byoung-taek Lee

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H05H1/00 ,  B05D3/06

CPC分类号： H01L28/60

摘要： A method for fabricating an integrated circuit capacitor includes the steps of forming a first electrode on a microelectronic substrate, and plasma treating the first electrode with a with a plasma of a gas including nitrogen and oxygen. A dielectric film is formed on the plasma treated first electrode opposite the microelectronic substrate. A second electrode is formed on the dielectric film opposite the plasma treated first electrode.

摘要翻译： 一种用于制造集成电路电容器的方法包括以下步骤：在微电子衬底上形成第一电极，以及用包括氮和氧的气体等离子体等离子体处理第一电极。 在与微电子衬底相对的等离子体处理的第一电极上形成电介质膜。 在与等离子体处理的第一电极相对的电介质膜上形成第二电极。

公开(公告)号：US06998200B2

公开(公告)日：2006-02-14

申请号：US10404398

申请日：2003-04-01

申请人： Byoung-taek Lee

发明人： Byoung-taek Lee

IPC分类号： G01F9/00

CPC分类号： G21K1/062 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/24 ,  G03F1/38 ,  G03F1/48

摘要： A reflection photomask includes a reflection layer on a substrate, an absorber pattern on the reflection layer, and a capping layer on the reflection layer. The capping layer may be selected to decrease a reflectivity of the reflection photomask by less than about 20% of the reflectivity of the reflection layer.

公开(公告)号：US06284589B1

公开(公告)日：2001-09-04

申请号：US09392906

申请日：1999-09-09

申请人： Han-jin Lim ,  Byoung-taek Lee

发明人： Han-jin Lim ,  Byoung-taek Lee

IPC分类号： H01L218242

CPC分类号： H01L21/76831 ,  H01L21/76802 ,  H01L21/76844 ,  H01L27/10855 ,  H01L28/55 ,  H01L28/91

摘要： In accordance with the present invention, a method of fabricating a concave capacitor is provided. The concave capacitor of the present invention includes an adhesion spacer is formed between a concave pattern comprising an interlayer dielectric film and a lower electrode is provided. In the concave capacitor fabricating method, an interlayer dielectric film is formal semiconductor substrate. A concave pattern having a storage node e exposing part of the upper surface of the semiconductor substrate is form by patterning the interlayer dielectric film. An adhesion spacer is formed on t sidewall of the concave pattern exposed by the storage node hole. A lower electrode to cover the adhesion spacer and the upper surface of the semiconductor substrate exposed by the storage node hole is formed in the storage node hole

摘要翻译： 根据本发明，提供一种制造凹电容器的方法。 本发明的凹电容器包括在包括层间绝缘膜和下电极的凹形图案之间形成粘合间隔物。 在凹电容器制造方法中，层间电介质膜是正式的半导体衬底。 具有露出半导体衬底的上表面的部分的存储节点e的凹形图案是通过图案化层间绝缘膜而形成的。 在由存储节点孔露出的凹形图案的t侧壁上形成粘合间隔物。 在存储节点孔中形成有用于覆盖粘合间隔物的下电极和由存储节点孔露出的半导体衬底的上表面

公开(公告)号：US06828190B2

公开(公告)日：2004-12-07

申请号：US09276803

申请日：1999-03-26

申请人： Byoung-taek Lee ,  Ki-hoon Lee

发明人： Byoung-taek Lee ,  Ki-hoon Lee

IPC分类号： H01L218242

CPC分类号： H01L28/82

摘要： A method of manufacturing a capacitor includes sequentially forming a storage electrode, a high dielectric layer, a plate electrode, and an interdielectric layer over a semiconductor substrate. A first post-annealing of the substrate is performed under an inert atmosphere at a first temperature, and then a second post-annealing is performed at a second temperature. The first and second post annealings can be performed after forming the high dielectric layer, the plate electrode, or the interdielectric layer, or any combination thereof, as long as the second post-annealing is performed after the first post-annealing. The post-annealings are not necessarily performed in a same place or stage. The first temperature may be about 600° C. to 900° C., and the second temperature about 100° C. to 600° C. As a result, the dielectric constant of the high dielectric layer is increased, and leakage current is reduced.

摘要翻译： 制造电容器的方法包括在半导体衬底上顺序形成存储电极，高电介质层，平板电极和电介质层。 在第一温度下在惰性气氛下进行基材的第一次后退火，然后在第二温度下进行第二次后退火。 第一和第二后退火可以在形成高介电层，平板电极或介电层之后进行，或者其任何组合，只要在第一次后退火之后进行第二次后退火即可。 后退火不一定在相同的地方或阶段进行。 第一温度可以为约600℃至900℃，第二温度为约100℃至600℃。结果，高介电层的介电常数增加，泄漏电流降低 。

公开(公告)号：US06180970B2

公开(公告)日：2001-01-30

申请号：US08909923

申请日：1997-08-12

申请人： Cheol-seong Hwang ,  Byoung-taek Lee

发明人： Cheol-seong Hwang ,  Byoung-taek Lee

IPC分类号： H01L2994

CPC分类号： H01L28/60 ,  H01L21/76895 ,  H01L28/55

摘要： A microelectronic device includes an insulating layer on a microelectronic substrate wherein the insulating layer has a contact hole therein exposing a portion of the microelectronic substrate. A first capacitor electrode is provided on a surface of the insulating layer opposite the microelectronic substrate and adjacent the contact hole wherein a lower portion of the first capacitor electrode extends into the contact hole below the surface of the insulating layer. A ferroelectric layer is provided on the first capacitor electrode, and a second capacitor electrode is provided on the ferroelectric layer. Related methods and memory devices are also discussed.

摘要翻译： 微电子器件包括在微电子衬底上的绝缘层，其中绝缘层在其中具有暴露微电子衬底的一部分的接触孔。 第一电容器电极设置在绝缘层的与微电子衬底相对的表面上并且邻近接触孔，其中第一电容器电极的下部延伸到绝缘层的表面下方的接触孔中。 在第一电容器电极上设置有铁电体层，在铁电体层上设置第二电容电极。 还讨论了相关方法和存储器件。

公开(公告)号：US06599806B2

公开(公告)日：2003-07-29

申请号：US09863729

申请日：2001-05-22

申请人： Byoung-taek Lee

发明人： Byoung-taek Lee

IPC分类号： H01L2120

CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L27/10852 ,  H01L28/55

摘要： A method for manufacturing a capacitor for a semiconductor device, the method includes forming a first interlayer dielectric film pattern on a semiconductor substrate, with the interlayer dielectric film pattern having a first contact hole to expose a portion of the semiconductor substrate through the first contact hole. A contact plug is formed to fill the first contact hole and connect to the semiconductor substrate. A diffusion barrier layer pattern is formed on the contact plug, and a first conductive film pattern is formed on the diffusion layer pattern. Next a second interlayer dielectric film pattern is formed on the first dielectric film pattern and the first conductive film pattern. The second interlayer dielectric film pattern includes a second contact hole that exposes a top surface of the first conductive film pattern. A second conductive film pattern is formed on the first conductive film pattern which is exposed through the second conductive film pattern and a third conductive film is formed on the dielectric film.

摘要翻译： 一种半导体器件用电容器的制造方法，其特征在于，在所述半导体基板上形成第一层间电介质膜图案，所述层间电介质膜图案具有第一接触孔，以通过所述第一接触孔露出所述半导体基板的一部分 。 形成接触插塞以填充第一接触孔并连接到半导体衬底。 在接触插塞上形成扩散阻挡层图案，并且在扩散层图案上形成第一导电膜图案。 接下来，在第一电介质膜图案和第一导电膜图案上形成第二层间电介质膜图案。 第二层间电介质膜图案包括暴露第一导电膜图案的顶表面的第二接触孔。 在通过第二导电膜图案曝光的第一导电膜图案上形成第二导电膜图案，并且在该电介质膜上形成第三导电膜。

公开(公告)号：US06239461B1

公开(公告)日：2001-05-29

申请号：US09245777

申请日：1999-02-05

申请人： Byoung-taek Lee

发明人： Byoung-taek Lee

IPC分类号： H01L27108

CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L27/10852 ,  H01L28/55

摘要： A capacitor of a semiconductor device includes a first interlayer dielectric film pattern formed on a semiconductor substrate and having a first contact hole therein and a contact plug buried in the first contact hole and electrically connected to the semiconductor substrate. A diffusion barrier layer pattern is formed on the contact plug, and a first conductive film pattern is formed on the diffusion barrier layer pattern for preventing the oxidization of the diffusion barrier layer pattern. A second interlayer dielectric pattern having a second contact hole exposing the surface of the first conductive film pattern is formed on the first interlayer dielectric film pattern and the first conductive film pattern. A second conductive film pattern used as the lower electrode of a capacitor is buried in the second contact hole and connected to the first conductive film pattern. A high dielectric film and a third conductive film pattern used as the upper electrode of the capacitor are sequentially formed so as to surround the second conductive film pattern. The first conductive film pattern is formed of a platinum group metal or a conductive oxide including the platinum group metal. According to the present invention, it is possible to prevent the increase of a contact resistance since the first conductive pattern prevents diffusion barrier layer pattern from oxidizing.

摘要翻译： 半导体器件的电容器包括形成在半导体衬底上并具有第一接触孔的第一层间电介质膜图案和埋在第一接触孔中并与半导体衬底电连接的接触插塞。 在接触塞上形成扩散阻挡层图案，并且在扩散阻挡层图案上形成第一导电膜图案，以防止扩散阻挡层图案的氧化。 在第一层间电介质膜图案和第一导电膜图案上形成具有暴露第一导电膜图案的表面的第二接触孔的第二层间电介质图案。 用作电容器的下电极的第二导电膜图案被掩埋在第二接触孔中并连接到第一导电膜图案。 依次形成用作电容器的上部电极的高电介质膜和第三导电膜图案，以包围第二导电膜图案。 第一导电膜图案由铂族金属或包含铂族金属的导电氧化物形成。 根据本发明，由于第一导电图案防止扩散阻挡层图案氧化，可以防止接触电阻的增加。

公开(公告)号：US5940705A

公开(公告)日：1999-08-17

申请号：US974084

申请日：1997-11-19

申请人： Byoung-taek Lee ,  Cheol-seong Hwang

发明人： Byoung-taek Lee ,  Cheol-seong Hwang

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/00 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11 ,  H01L27/115 ,  H01L29/78 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/11597 ,  H01L29/78391

摘要： Methods of forming floating-gate ferroelectric random-access-memory (FFRAM) devices include the steps of forming vertically integrated FFRAM unit cells having floating-gate transistors and access transistors positioned at different levels on a semiconductor substrate to increase the density at which the unit cells may be integrated. Preferred methods include the steps of forming a first transistor having opposing floating and control gate electrodes, at a surface of a semiconductor substrate, and then forming a first insulating layer having a first contact hole therein, on the first transistor. The first transistor comprises a layer of ferroelectric material between the floating and control gate electrodes, which can be polarized in respective first and second states to retain logic 1 and logic 0 data. Steps are then performed to form a first electrical interconnect (e.g., conductive plug) in the first contact hole and electrically coupled to the control gate electrode. Then, a series of steps are performed to form a vertically integrated second transistor on the first insulating layer. Here, the second transistor is formed as a field effect transistor having a drain region electrically coupled to the control gate of the first transistor by the first electrical interconnect. The steps of forming a second transistor may include the steps of forming a silicon-on-insulator (SOI) substrate on the first insulating layer, forming a gate electrode on the silicon portion of the SOI substrate, and then forming source, drain and channel regions in the silicon portion of the SOI substrate.

摘要翻译： 形成浮栅铁电随机存取存储器（FFRAM）器件的方法包括以下步骤：在半导体衬底上形成具有浮置栅极晶体管和位于不同电平的存取晶体管的垂直集成的FFRAM单元，以增加单元 单元可以被集成。 优选的方法包括在半导体衬底的表面上形成具有相对的浮动和控制栅电极的第一晶体管的步骤，然后在第一晶体管上形成其中具有第一接触孔的第一绝缘层。 第一晶体管包括在浮动栅极和控制栅电极之间的铁电材料层，其可以在相应的第一和第二状态下被极化以保持逻辑1和逻辑0数据。 然后执行步骤以在第一接触孔中形成第一电互连（例如，导电插塞）并电耦合到控制栅电极。 然后，执行一系列步骤以在第一绝缘层上形成垂直集成的第二晶体管。 这里，第二晶体管形成为具有通过第一电互连电耦合到第一晶体管的控制栅极的漏极区域的场效应晶体管。 形成第二晶体管的步骤可以包括在第一绝缘层上形成绝缘体上硅（SOI）衬底的步骤，在SOI衬底的硅部分上形成栅电极，然后形成源极，漏极和沟道 SOI衬底的硅部分的区域。