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18 条记录 (耗时 0.027 秒)

    Phase change memory device and memory cell array thereof
    1.
    发明授权
    Phase change memory device and memory cell array thereof 有权
    相变存储器件及其存储单元阵列

    公开(公告)号：US07453722B2

    公开(公告)日：2008-11-18

    申请号：US11319364

    申请日：2005-12-29

    申请人： Byung-Gil Choi ,  Jong-Soo Seo ,  Young-Kug Moon ,  Bo-Tak Lim ,  Su-Yeon Kim

    发明人： Byung-Gil Choi ,  Jong-Soo Seo ,  Young-Kug Moon ,  Bo-Tak Lim ,  Su-Yeon Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2213/72 ,  G11C2213/79

    摘要： A phase change memory device is provided which includes a memory cell array including a plurality of memory cells, and a write driver for supplying a program current to the memory cell array through a global bitline. The memory cell array includes first and second cell regions, a first local bitline connected to the first cell region, a second local bitline connected to the second cell region, and a select region disposed between the first and second cell regions and supplying the program current supplied through the global bitline to the first and second local bitlines in response to a local select signal.

    摘要翻译： 提供了一种相变存储器件，其包括包括多个存储器单元的存储单元阵列，以及用于通过全局位线将编程电流提供给存储单元阵列的写入驱动器。 存储单元阵列包括第一和第二单元区域，连接到第一单元区域的第一本地位线，连接到第二单元区域的第二本地位线，以及设置在第一单元区域和第二单元区域之间并提供程序电流的选择区域 通过全局位线提供响应于本地选择信号的第一和第二本地位线。

    Phase change memory device and memory cell array thereof
    2.
    发明申请
    Phase change memory device and memory cell array thereof 有权
    相变存储器件及其存储单元阵列

    公开(公告)号：US20070133268A1

    公开(公告)日：2007-06-14

    申请号：US11319364

    申请日：2005-12-29

    申请人： Byung-Gil Choi ,  Jong-Soo Seo ,  Young-Kug Moon ,  Bo-Tak Lim ,  Su-Yeon Kim

    发明人： Byung-Gil Choi ,  Jong-Soo Seo ,  Young-Kug Moon ,  Bo-Tak Lim ,  Su-Yeon Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2213/72 ,  G11C2213/79

    摘要： A phase change memory device is provided which includes a memory cell array including a plurality of memory cells, and a write driver for supplying a program current to the memory cell array through a global bitline. The memory cell array includes first and second cell regions, a first local bitline connected to the first cell region, a second local bitline connected to the second cell region, and a select region disposed between the first and second cell regions and supplying the program current supplied through the global bitline to the first and second local bitlines in response to a local select signal.

    摘要翻译： 提供了一种相变存储器件，其包括包括多个存储器单元的存储单元阵列，以及用于通过全局位线将编程电流提供给存储单元阵列的写入驱动器。 存储单元阵列包括第一和第二单元区域，连接到第一单元区域的第一本地位线，连接到第二单元区域的第二本地位线，以及设置在第一单元区域和第二单元区域之间并提供程序电流的选择区域 通过全局位线提供响应于本地选择信号的第一和第二本地位线。

    Test element group structures having 3 dimensional SRAM cell transistors
    5.
    发明申请
    Test element group structures having 3 dimensional SRAM cell transistors 审中-公开
    具有3维SRAM单元晶体管的测试元件组结构

    公开(公告)号：US20060163571A1

    公开(公告)日：2006-07-27

    申请号：US11331232

    申请日：2006-01-12

    申请人： Bo-Tak Lim ,  Jong-Soo Seo

    发明人： Bo-Tak Lim ,  Jong-Soo Seo

    IPC分类号： H01L23/58

    CPC分类号： H01L22/34 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104

    摘要： A test element group structure having 3-dimensional SRAM cell transistors includes a bulk metal-oxide-semiconductor (MOS) transistor formed at a semiconductor substrate and a first interlayer insulating layer covering the bulk MOS transistor. A lower thin film transistor is disposed on the first interlayer insulating layer, and the lower thin film transistor is covered with a second interlayer insulating layer. An upper thin film transistor is disposed on the second interlayer insulating layer, and the upper thin film transistor is covered with a third interlayer insulating layer. A metal node plug is disposed to pass through the first to third interlayer insulating layers. The metal node plug electrically connects a first impurity region of the bulk MOS transistor, a first impurity region of the lower thin film transistor, and a first impurity region of the upper thin film transistor with each other.

    摘要翻译： 具有3维SRAM单元晶体管的测试元件组结构包括形成在半导体衬底上的体金属氧化物半导体（MOS）晶体管和覆盖体MOS晶体管的第一层间绝缘层。 下部薄膜晶体管设置在第一层间绝缘层上，下部薄膜晶体管被第二层间绝缘层覆盖。 上部薄膜晶体管设置在第二层间绝缘层上，上部薄膜晶体管被第三层间绝缘层覆盖。 金属节点插头设置成穿过第一至第三层间绝缘层。 金属节点插塞将本体MOS晶体管的第一杂质区域，下部薄膜晶体管的第一杂质区域和上部薄膜晶体管的第一杂质区域彼此电连接。

    APPARATUS AND METHOD FOR ALLOCATING RESOURCES IN MOBILE COMMUNICATION SYSTEM
    6.
    发明申请
    APPARATUS AND METHOD FOR ALLOCATING RESOURCES IN MOBILE COMMUNICATION SYSTEM 有权
    在移动通信系统中分配资源的装置和方法

    公开(公告)号：US20080031216A1

    公开(公告)日：2008-02-07

    申请号：US11833036

    申请日：2007-08-02

    申请人： Jong-Hyeuk LEE ,  Sang-Boh Yun ,  Dae-Young Park ,  Jong-Soo Seo ,  Won-Kyu Paik

    发明人： Jong-Hyeuk LEE ,  Sang-Boh Yun ,  Dae-Young Park ,  Jong-Soo Seo ,  Won-Kyu Paik

    IPC分类号： H04J1/00

    CPC分类号： H04L5/0007 ,  H04L1/0002 ,  H04L5/0037 ,  H04L5/006 ,  H04L5/0062 ,  H04W72/044

    摘要： Provided are an apparatus and method for allocating resources in a mobile communication system. The apparatus includes a modulating/coding unit for modulating transmission data of one or more users according to a predetermined modulation scheme and for outputting a complex signal; a 2-Dimensional (2D)/1-Dimensional (1D) converter for converting the complex signal into a 1D signal; and a re-modulator for reconstructing the 1D signal to a 2D signal and for allocating two components of the 2D signal to two different frequency bands.

    摘要翻译： 提供了一种用于在移动通信系统中分配资源的装置和方法。 该装置包括：调制/编码单元，用于根据预定的调制方案调制一个或多个用户的发送数据，并输出复数信号; 用于将复数信号转换为1D信号的二维（2D）/一维（1D）转换器; 以及用于将1D信号重建为2D信号并将2D信号的两个分量分配给两个不同频带的再调制器。

    Symbol timing synchronization method for OFDM based communication system
    7.
    发明申请
    Symbol timing synchronization method for OFDM based communication system 审中-公开
    基于OFDM的通信系统的符号定时同步方法

    公开(公告)号：US20050180516A1

    公开(公告)日：2005-08-18

    申请号：US11047422

    申请日：2005-01-31

    申请人： Sang-Jin Lee ,  Jong-Soo Seo ,  Eung-Sun Kim ,  Jong-Hyeuk Lee

    发明人： Sang-Jin Lee ,  Jong-Soo Seo ,  Eung-Sun Kim ,  Jong-Hyeuk Lee

    IPC分类号： H04J11/00 ,  H04K1/10 ,  H04L27/26

    CPC分类号： H04L27/2662 ,  H04L27/2607 ,  H04L27/2678

    摘要： A synchronization method in an OFDM based communication system. A transmitting side generates and transmits an OFDM symbol having a constant cyclic prefix, independent of time domain data symbols that are to be transmitted. A receiving side estimates a timing synchronization error based on the known cyclic prefix. Because the timing synchronization error is estimated based on the constant cyclic prefix, which is always known, a highly reliable correlation is achieved, thereby improving the accuracy of synchronization.

    摘要翻译： 基于OFDM的通信系统中的同步方法。 发送侧生成并发送具有恒定循环前缀的OFDM符号，与待发送的时域数据符号无关。 接收侧基于已知的循环前缀来估计定时同步误差。 由于定时同步误差是基于始终是已知的恒定循环前缀来估计的，所以实现了高度可靠的相关性，从而提高了同步的准确性。

    Variable resistance memory device
    10.
    发明授权
    Variable resistance memory device 有权
    可变电阻存储器件

    公开(公告)号：US07580278B2

    公开(公告)日：2009-08-25

    申请号：US11868992

    申请日：2007-10-09

    申请人： Beak-Hyung Cho ,  Jong-Soo Seo ,  Won-Seok Lee

    发明人： Beak-Hyung Cho ,  Jong-Soo Seo ,  Won-Seok Lee

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79

    摘要： A variable resistance memory device includes a memory cell array having a plurality of memory cells, a write driver which supplies a step-down set current to the memory cells, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver. The set program control circuit controls the duration of the step-down set current in accordance with at least one of data contained in an mode register set (MRS) and a conductive state of a fuse element.

    摘要翻译： 可变电阻存储器件包括具有多个存储器单元的存储单元阵列，一个写入驱动器，其将降压设定电流提供给存储器单元，其中降压设定电流包括多个连续的步骤，其降低电流幅度 以及控制由写入驱动器提供的降压设定电流的持续时间的设定程序控制电路。 设定程序控制电路根据包含在模式寄存器组（MRS）和熔丝元件的导通状态中的至少一个数据来控制降压设定电流的持续时间。