公开(公告)号：US11722291B1

公开(公告)日：2023-08-08

申请号：US17399953

申请日：2021-08-11

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Steven Ho ,  Gopi Krishnamurthy ,  Anish Mathew

IPC: H04L9/06 ,  H04L9/08

CPC classification number: H04L9/0618 ,  H04L9/065 ,  H04L9/0816 ,  H04L9/0869

Abstract: A method of low-latency and encrypted hardware layer communication includes calculating, by an encryption circuit of a communication bridge controller, a pre-calculated encryption keys corresponding to a block encryptor of the encryption circuit, each block encryptor configured to use a corresponding pre-calculated encryption key to encrypt a corresponding unencrypted data block of a data transmission having one or more unencrypted data blocks, storing the one or more pre-calculated encryption keys in an encryption key memory associated with the communication bridge, for each unecrypted data block, encrypting the unencrypted data block using the corresponding pre-calculated encryption key to generate an encrypted data block and an authentication code block for the unencrypted data block, aggregating one or more encrypted data blocks into an encrypted data transmission, and generating an authenticated code corresponding to the encrypted data transmission based upon each of the authentication code blocks of each of the encrypted data blocks.

公开(公告)号：US10176126B1

公开(公告)日：2019-01-08

申请号：US14754508

申请日：2015-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Bikram Banerjee ,  Anish Mathew

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/42

Abstract: Disclosed are peripheral component interconnect (PCI) implementations and methods for implementing PCI implementations handling posted transaction layer packets (TLPs) and completion TLPs. PCI implementations include one or more receive buffers storing completion TLPs and posted TLPs, a set of write and read pointers for the receive buffers, a token manager to associate ordering tokens with posted TLPs, and a pointer-based ordering mechanism to determine an order for handling posted and completion TLPs. PCI implementations may further include an identification-based ordering mechanism to revise the order. The methods identify a completion TLP and multiple posted TLPs, associate a posted TLP with an ordering token, and determine the order for handling the completion and posted TLPs with at least the pointer-based ordering mechanism. The methods may further optionally revise the order with at least the identification-based ordering mechanism.

公开(公告)号：US11128410B1

公开(公告)日：2021-09-21

申请号：US16515556

申请日：2019-07-18

Applicant: Cadence Design Systems, Inc.

Inventor： Chetan Paragaonkar ,  Gopi Krishnamurthy ,  Anish Mathew ,  Raveendra Pai Gopalakrishna ,  Anujan Varma

IPC: H04L1/18 ,  G06F13/38 ,  H04L12/801

Abstract: Embodiments disclosed are directed to methods for scheduling packets. According to example embodiments the method includes receiving, using a first layer in a communication protocol, a first request from a second layer in the communication protocol. The first request indicates to the first layer to output a data stream that includes a first location for the second layer to include a first control packet. The first layer is at a higher level of abstraction than the second layer. The method further includes transmitting, using the first layer, a first response to the second layer. The first response is based on the first request, and the first response identifies the first location in the data stream and a time of occurrence of the first location in the data stream.

公开(公告)号：US08880980B1

公开(公告)日：2014-11-04

申请号：US13686612

申请日：2012-11-27

Applicant: Cadence Design Systems, Inc.

Inventor： Anish Mathew ,  Sandeep Brahmadathan ,  Raveendra Pai G.

IPC: G11C29/00 ,  H03M13/05 ,  H03M13/15

CPC classification number: H03M13/15 ,  H03M13/13 ,  H03M13/152 ,  H03M13/27

Abstract: A system and method for expeditious transfer of data from a source device to a destination device in error corrected manner are provided. The system and method avoid the substantial delay in utilizing an intermediate buffer, determining error, and remediating the detected errors before even initializing a transfer of an input data from the source device to the destination device. Upon completion of error correction, only those portions corrected are retransmitted to the destination memory rather than the complete corrected input data. A by-pass section is provided for copying input data to the destination memory with at least a degree of parallelism with the error detection of the input data delivered to a parallel buffer coupled with the correction section by a splitter section.

Abstract translation: 提供了一种用于以错误校正的方式从源设备快速传送数据到目的地设备的系统和方法。 该系统和方法在初始化从源设备到目的设备的输入数据传输之前避免了利用中间缓冲器的实质性延迟，确定错误以及修复检测到的错误。 在完成纠错后，只有那些被校正的部分被重新发送到目的地存储器而不是完整的校正输入数据。 提供了一个旁路部分，用于将输入数据复制到目的地存储器，至少具有与通过分离器部分与校正部分耦合的并行缓冲器的输入数据的错误检测的并行度。