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公开(公告)号：US11799426B2
公开(公告)日：2023-10-24
申请号：US17537619
申请日：2021-11-30
Inventor： Johnny Klarenbeek , David P. Singleton , Morgan T. Prior , Jonathan T. Wigner , Christopher M. Dougherty , Qi Cai , Anindya Bhattacharya
CPC classification number: H03F1/0233 , H03F3/217 , H03F2200/03 , H03F2200/105
Abstract: Class D amplifier circuitry comprising: input buffer circuitry configured to receive a first digital input signal modulated according to a first modulation scheme in which the digital input signal can take a first plurality N of discrete signal levels; analog modulator circuitry configured to generate an analog modulated signal based on an analog output signal output by the input buffer circuitry; and quantizer circuitry configured to generate an output signal based on the analog modulated signal, wherein the output signal is modulated according to a second modulation scheme in which the output signal can take a second plurality M of discrete signal levels, wherein the second plurality M is greater than the first plurality N.
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公开(公告)号：US11782101B2
公开(公告)日：2023-10-10
申请号：US16987257
申请日：2020-08-06
Inventor： Prashanth Drakshapalli , John L. Melanson , Anindya Bhattacharya , Seung Bae Lee
Abstract: A data acquisition system (DAS) for acquiring data from a Hall effect sensor includes one or more state variables, a multiplexer that periodically rotates a signal from the Hall effect sensor, and a controller that resets the one or more state variables in synchronization with rotation of the signal. The state variables may be digital states in a digital memory or voltages of capacitors the controller forces to a reset voltage. The state variables may be included in a noise-shaping SAR ADC, a delta-sigma ADC, a digital filter, an integrator, an analog filter, a VCO, an incremental ADC or an auxiliary ADC-assisted incremental ADC, or an auxiliary ADC of the DAS.
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公开(公告)号：US20170163252A1
公开(公告)日：2017-06-08
申请号：US14962615
申请日：2015-12-08
Inventor： Vaibhav Pandey , John L. Melanson , Anindya Bhattacharya
IPC: H03K5/24 , H03K3/3565
CPC classification number: H03K5/2481 , H03K3/02337 , H03K3/3565
Abstract: In accordance with embodiments of the present disclosure, a comparator may include a transconductance stage having an input configured to receive an input voltage and generate an intermediate current responsive to the input voltage, a hysteretic current source configured to generate a hysteretic current, an output stage configured to generate an output signal based at least on the intermediate current, and a switch responsive to the output stage and configured to combine the intermediate current and the hysteretic current to generate a combined current, such that the output stage generates the output signal based at least on the intermediate current and the hysteretic current when output signal has a first value.
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公开(公告)号：US11316523B1
公开(公告)日：2022-04-26
申请号：US17308741
申请日：2021-05-05
Inventor： Saurabh Singh , Jaimin Mehta , Sriram Balasubramanian , Anindya Bhattacharya
Abstract: A system may include a digitally-controlled oscillator configured to generate an output clock signal based on a control signal received at an input of the digitally-controlled oscillator and a control circuit configured to calculate an error signal between the output clock signal and an external reference clock signal, filter the error signal to generate a correction signal, generate the control signal based on the correction signal, and switch between a first mode of operation and a second mode of operation without artifacts on the correction signal during switching between the first mode and the second mode.
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公开(公告)号：US11290120B2
公开(公告)日：2022-03-29
申请号：US16987254
申请日：2020-08-06
Inventor： Seung Bae Lee , John L. Melanson , Anindya Bhattacharya , Prashanth Drakshapalli
Abstract: A data acquisition system (DAS) for processing an input signal from a resistive sensor (e.g., Hall effect sensor) includes a sensor signal path that digitizes the input signal. An input impedance of the sensor signal path attenuates the input signal. A gain error corrector applies a gain error correction factor in a digital domain of the DAS to the digitized input signal to compensate for a loading effect to the resistive sensor. The sensor signal path includes an inverting amplifier that provides low distortion for the input signal and an ADC (e.g., delta-sigma, SAR, pipelined, auxiliary) that digitizes the input signal. A sensor characterization path digitizes the sensor resistance which the gain error corrector uses, along with the inverting amplifier input impedance, to calculate the gain error correction factor.
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Patent Agency Ranking
公开(公告)号：US11641558B2
公开(公告)日：2023-05-02
申请号：US17108433
申请日：2020-12-01
Inventor： Anindya Bhattacharya , Bhoodev Kumar , Jaimin Mehta , Yongsheng Shi , Aleksey S. Khenkin , John L. Melanson
IPC: H04R29/00
Abstract: A method and apparatus for detecting a microphone condition of a microphone, the method comprising: applying an electrical stimulus to a microphone; measuring an electrical response to the electrical stimulus at the microphone; comparing the electrical response to an expected response; and determining the microphone condition based on the comparison.
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公开(公告)号：US11489534B1
公开(公告)日：2022-11-01
申请号：US17498183
申请日：2021-10-11
Inventor： Seung Bae Lee , Sunny Bhagia , Jaiminkumar Mehta , Anindya Bhattacharya , John L. Melanson
Abstract: Digital-to-analog converter (DAC) architecture, comprising: a matrix DAC array comprising a plurality of cells arranged in a first dimension and a second dimension, each cell comprising a local decoder configured to transition the cell between at least two states; and decoding circuitry configured to: receive a digital input signal; and control the plurality of local decoders based on a received digital input signal, wherein each incremental change in the digital input signal results in a transition of a single cell of the plurality of cells such that the plurality of cells transition in sequence, the sequence of transitions of the plurality of cells defining a path through the DAC array; wherein when the path proceeds in the first dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time; and wherein when the path proceeds in the second dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time.
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公开(公告)号：US20180335458A1
公开(公告)日：2018-11-22
申请号：US15598582
申请日：2017-05-18
Inventor： John L. Melanson , Anindya Bhattacharya , Axel Thomsen , Eric Smith , Vamsikrishna Parupalli , Mark May , Johann Gaboriau , Junsong Li
CPC classification number: G01D5/24 , G01R27/2605
Abstract: Sensing electronics may be used to measure capacitance of components, such as speakers in mobile devices. A sensing circuit may include a charge-sense front end with sine wave excitation, an analog-to-digital conversion block, and a digital demodulator. The component being measured by the sensing electronics may be excited by a high-frequency sine wave excitation. The digitization of the output from the component may be performed using a bandpass filter synchronized with the excitation signal by centering the bandpass filter near (e.g., within 5% of) the frequency of the excitation signal.
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公开(公告)号：US20250147713A1
公开(公告)日：2025-05-08
申请号：US18500224
申请日：2023-11-02
Inventor： Gaofeng Fan , Qi Cai , John B. Bowlerwell , Richard Turkson , Anindya Bhattacharya , Bhoodev Kumar
IPC: G06F3/16
Abstract: Circuit techniques reduce or prevent audible artifacts in a Universal Audio Jack (UAJ) interface circuit, improving handling of mis-configuration/mis-attachment of devices. The interface includes at least one terminal for accepting an audio input signal or providing an audio line output signal coupled to an input or output of a first audio circuit. The first audio circuit operates from a low voltage domain and receives the audio input signal or provides the audio line output signal. A second circuit operates from a higher voltage domain and a switching circuit couples the at least one terminal to the second circuit. The output is slew-rate controlled to control a transition time of the output, so that audible artifacts in the audio input signal or the audio line output signal that could be generated by the switching circuit connecting the second circuit to the at least one terminal are avoided.
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公开(公告)号：US11119524B1
公开(公告)日：2021-09-14
申请号：US16815505
申请日：2020-03-11
Inventor： Christopher M. Dougherty , Anindya Bhattacharya , Vaibhav Pandey , Ying Ou
IPC: G05F3/26
Abstract: A selectable output current mirror may include a reference leg configured to generate a reference current, an output leg electrically coupled to the reference leg in a manner such that the output leg is configured to generate at an output of the output leg an output current proportional to the reference current, wherein the output leg comprises an output leg transistor, a drain path switch coupled between a first non-gate terminal of the output leg transistor and the output of the output leg, and a series combination of a degeneration resistor and a degeneration path switch coupled between a second non-gate terminal of the output leg transistor and a voltage source to the selectable output current mirror. The selectable output current mirror may also include switch control circuitry configured to selectively enable and disable the output leg from generating the output current by selectively enabling and disabling the drain path switch and the degeneration path switch and glitch mitigation circuitry coupled to the second non-gate terminal of the output leg transistor and configured to maintain the second non-gate terminal of the output leg transistor at a substantially-constant voltage during transitions between disabling of the degeneration path switch and enabling of the degeneration path switch.
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