公开(公告)号：US20220320432A1

公开(公告)日：2022-10-06

申请号：US17218608

申请日：2021-03-31

申请人： CROSSBAR, INC.

发明人： Sundar Narayanan ,  Wee Chen Gan ,  Natividad Vasquez, JR. ,  Wei Ti Lee

IPC分类号： H01L45/00 ,  H01L27/24

摘要： Resistive switching memory cells having filament-based switching mechanisms are provided. By way of example, resistive switching memory cells having resistive filaments constrained to a core of the cell are disclosed. In other examples, methods for fabricating resistive switching memory cells to constrain a conductive filament formed in the resistive switching memory cell to a central portion of core of the cell are disclosed.

公开(公告)号：US20150228893A1

公开(公告)日：2015-08-13

申请号：US14613585

申请日：2015-02-04

申请人： Crossbar, Inc.

发明人： Sundar Narayanan ,  Steve Maxwell ,  Natividad Vasquez, JR. ,  Harry Yue Gee

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1233 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/249 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/124 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

摘要： A memory cell that includes a first metal layer formed over a substrate is provided. The substrate includes one or more complementary metal-oxide semiconductor devices. The memory cell also includes a via device that connects at least a portion of the first metal layer and at least another portion of a second metal layer. The first metal layer has a first thickness having an edge thereof that serves as an electrode for a memory cell formed by the via device. The memory cell scales as a function of the first thickness and at least in part independent of a minimum feature size of the memory device.

摘要翻译： 提供了包括在衬底上形成的第一金属层的存储单元。 衬底包括一个或多个互补金属氧化物半导体器件。 存储单元还包括连接第一金属层的至少一部分和第二金属层的至少另一部分的通孔装置。 第一金属层具有第一厚度，其第一厚度具有用作由通孔装置形成的存储单元的电极的边缘。 存储器单元按照第一厚度的尺寸缩放，并且至少部分地独立于存储器件的最小特征尺寸。

公开(公告)号：US20160351625A1

公开(公告)日：2016-12-01

申请号：US14726071

申请日：2015-05-29

申请人： Crossbar, Inc.

发明人： Harry Yue Gee ,  Tanmay Kumar ,  Natividad Vasquez, JR. ,  Steven Patrick Maxwell ,  Sundar Narayanan

IPC分类号： H01L27/24 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/265

CPC分类号： H01L29/7827 ,  H01L27/2436 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66621 ,  H01L45/16

摘要： A recessed high voltage metal oxide semiconductor (MOS) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a resistive switching device connected to the recessed MOS transistor. The recessed MOS transistor provides for an increased channel length relative to the transistor size in comparison to a traditional MOS transistor. This allows for a decreased memory cell size while maintaining comparable electrical parameters (threshold voltage, channel length, and leakage) than would otherwise be possible. The recessed MOS transistor can be made as either a NMOS or PMOS device using n-type or p-type materials respectively, where the channel, or inversion layer, is formed by electrons (NMOS) or holes (PMOS) between the source and drain in the transistor.

摘要翻译： 提供了一种用于两端存储单元的凹陷高压金属氧化物半导体（MOS）晶体管。 两端存储单元可以包括连接到凹陷MOS晶体管的电阻开关器件。 与传统的MOS晶体管相比，凹陷式MOS晶体管相对于晶体管尺寸提供增加的沟道长度。 这允许减小的存储器单元尺寸，同时保持与否则可能的可比较的电参数（阈值电压，沟道长度和泄漏）。 凹陷MOS晶体管可以分别使用n型或p型材料制成NMOS或PMOS器件，其中沟道或反型层由源极和漏极之间的电子（NMOS）或空穴（PMOS）形成 在晶体管中。

公开(公告)号：US20150318333A1

公开(公告)日：2015-11-05

申请号：US14636363

申请日：2015-03-03

申请人： Crossbar, Inc.

发明人： Sundar Narayanan ,  Steve Maxwell ,  Natividad Vasquez, JR. ,  Harry Yue Gee

IPC分类号： H01L27/24 ,  H01L21/768 ,  H01L23/532 ,  H01L45/00 ,  H01L23/522

CPC分类号： H01L45/1675 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L27/092 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

摘要： Providing for a memory device having a resistive switching memory integrated within backend layers of the memory device is described herein. By way of example, the resistive switching memory can be embedded memory such as cache, random access memory, or the like, in various embodiments. The resistive memory can be fabricated between various backend metallization schemes, including backend copper metal layers and in part utilizing one or more damascene processes. In some embodiments, the resistive memory can be fabricated in part with damascene processes and in part with subtractive etch processing, utilizing four or fewer photo-resist masks. Accordingly, the disclosure provides a relatively low cost, high performance embedded memory compatible with a variety of fabrication processes of integrated circuit foundries.

摘要翻译： 在此描述了具有集成在存储器件的后端层中的电阻式开关存储器的存储器件。 作为示例，在各种实施例中，电阻式交换存储器可以是诸如高速缓存，随机存取存储器等的嵌入式存储器。 电阻性存储器可以在各种后端金属化方案之间制造，包括后端铜金属层，并且部分地利用一个或多个镶嵌工艺。 在一些实施例中，电阻存储器可以部分地用镶嵌工艺制造，并且部分地利用减去蚀刻处理，利用四个或更少的光致抗蚀剂掩模制造。 因此，本公开提供了与集成电路铸造厂的各种制造工艺兼容的相对低成本，高性能的嵌入式存储器。

公开(公告)号：US20150243886A1

公开(公告)日：2015-08-27

申请号：US14587711

申请日：2014-12-31

申请人： Crossbar, Inc.

发明人： Sundar Narayanan ,  Steve Maxwell ,  Natividad Vasquez, JR. ,  Harry Yue Gee

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L27/2463 ,  H01L27/092 ,  H01L27/2436 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/148 ,  H01L45/16

摘要： Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.

摘要翻译： 提供了使用集成电路铸造工艺的电阻式存储器与互补金属氧化物半导体的单片集成。 提供了一种存储器件，其包括：包含一个或多个互补金属氧化物半导体器件的衬底;在衬底上形成的第一绝缘体层; 和单片堆叠。 整体堆叠包括在第一绝缘体层上作为单片工艺的一部分制造的多个层。 多层包括第一金属层，第二绝缘体层和第二金属层。 电阻存储器件结构形成在第二绝缘体层内并且在一个或多个互补金属氧化物半导体器件的热预算内。 电阻式存储器件结构被实现为支柱器件或通孔器件。 此外，第一金属层耦合到第二金属层。