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    Resistive random access memory (RRAM) cell and method for forming the RRAM cell
    1.
    发明授权
    Resistive random access memory (RRAM) cell and method for forming the RRAM cell 有权
    电阻随机存取存储器（RRAM）单元及形成RRAM单元的方法

    公开(公告)号：US09595670B1

    公开(公告)日：2017-03-14

    申请号：US14337111

    申请日：2014-07-21

    申请人： Crossbar, Inc.

    发明人： Harry Yue Gee ,  Steven Patrick Maxwell ,  Natividad Vasquez, Jr. ,  Sundar Narayanan

    IPC分类号： H01L21/336 ,  H01L45/00

    CPC分类号： H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1675

    摘要： A method includes patterning a layered structure comprising a monolithic stack including a bottom electrode surrounded by a dielectric material, a switching material, a barrier material, a dielectric hardmask, and a patterned photoresist formed above and adjacent to a portion of the dielectric hardmask. The patterning includes patterning the dielectric hardmask using a first etchant and employing the patterned photoresist as a mask, patterning the barrier material using a second etchant and employing a portion of the dielectric hardmask remaining after the patterning the dielectric hardmask as a mask, and patterning the switching material using ion milling or etching and employing the portion of the dielectric hardmask remaining after the patterning the barrier material as a mask.

    摘要翻译： 一种方法包括图案化的层状结构，其包括单片堆叠，其包括由介电材料包围的底部电极，开关材料，阻挡材料，电介质硬掩模和形成在电介质硬掩模的一部分上方并与其相邻的图案化光致抗蚀剂。 图案化包括使用第一蚀刻剂图案化介电硬掩模，并使用图案化的光致抗蚀剂作为掩模，使用第二蚀刻剂图案化阻挡材料，并且在图案化介电硬掩模作为掩模之后使用剩余的介电硬掩模的一部分， 使用离子研磨或蚀刻的开关材料，并且在将阻挡材料图案化为掩模之后使用剩余的电介质硬掩模的部分。

    RECESSED HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR TRANSISTOR FOR RRAM CELL
    2.
    发明申请
    RECESSED HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR TRANSISTOR FOR RRAM CELL 审中-公开
    用于RRAM电池的高压金属氧化物半导体晶体管

    公开(公告)号：US20160351625A1

    公开(公告)日：2016-12-01

    申请号：US14726071

    申请日：2015-05-29

    申请人： Crossbar, Inc.

    发明人： Harry Yue Gee ,  Tanmay Kumar ,  Natividad Vasquez, JR. ,  Steven Patrick Maxwell ,  Sundar Narayanan

    IPC分类号： H01L27/24 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/265

    CPC分类号： H01L29/7827 ,  H01L27/2436 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66621 ,  H01L45/16

    摘要： A recessed high voltage metal oxide semiconductor (MOS) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a resistive switching device connected to the recessed MOS transistor. The recessed MOS transistor provides for an increased channel length relative to the transistor size in comparison to a traditional MOS transistor. This allows for a decreased memory cell size while maintaining comparable electrical parameters (threshold voltage, channel length, and leakage) than would otherwise be possible. The recessed MOS transistor can be made as either a NMOS or PMOS device using n-type or p-type materials respectively, where the channel, or inversion layer, is formed by electrons (NMOS) or holes (PMOS) between the source and drain in the transistor.

    摘要翻译： 提供了一种用于两端存储单元的凹陷高压金属氧化物半导体（MOS）晶体管。 两端存储单元可以包括连接到凹陷MOS晶体管的电阻开关器件。 与传统的MOS晶体管相比，凹陷式MOS晶体管相对于晶体管尺寸提供增加的沟道长度。 这允许减小的存储器单元尺寸，同时保持与否则可能的可比较的电参数（阈值电压，沟道长度和泄漏）。 凹陷MOS晶体管可以分别使用n型或p型材料制成NMOS或PMOS器件，其中沟道或反型层由源极和漏极之间的电子（NMOS）或空穴（PMOS）形成 在晶体管中。

    Reduced diffusion in metal electrode for two-terminal memory
    3.
    发明授权
    Reduced diffusion in metal electrode for two-terminal memory 有权

    公开(公告)号：US10910561B1

    公开(公告)日：2021-02-02

    申请号：US15587560

    申请日：2017-05-05

    申请人： Crossbar, Inc.

    发明人： Steven Patrick Maxwell ,  Sung Hyun Jo

    IPC分类号： H01L45/00 ,  H01L27/24 ,  G11C13/00

    摘要： Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.

    Recessed high voltage metal oxide semiconductor transistor for RRAM cell
    4.
    发明授权
    Recessed high voltage metal oxide semiconductor transistor for RRAM cell 有权

    公开(公告)号：US10115819B2

    公开(公告)日：2018-10-30

    申请号：US14726071

    申请日：2015-05-29

    申请人： Crossbar, Inc.

    发明人： Harry Yue Gee ,  Tanmay Kumar ,  Natividad Vasquez, Jr. ,  Steven Patrick Maxwell ,  Sundar Narayanan

    IPC分类号： H01L29/423 ,  H01L27/24 ,  H01L29/78 ,  H01L45/00 ,  H01L29/66

    摘要： A recessed high voltage metal oxide semiconductor (MOS) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a resistive switching device connected to the recessed MOS transistor. The recessed MOS transistor provides for an increased channel length relative to the transistor size in comparison to a traditional MOS transistor. This allows for a decreased memory cell size while maintaining comparable electrical parameters (threshold voltage, channel length, and leakage) than would otherwise be possible. The recessed MOS transistor can be made as either a NMOS or PMOS device using n-type or p-type materials respectively, where the channel, or inversion layer, is formed by electrons (NMOS) or holes (PMOS) between the source and drain in the transistor.

    Methods for fabricating resistive memory device switching material using ion implantation
    5.
    发明授权
    Methods for fabricating resistive memory device switching material using ion implantation 有权
    使用离子注入制造电阻式存储器件开关材料的方法

    公开(公告)号：US09583701B1

    公开(公告)日：2017-02-28

    申请号：US14213953

    申请日：2014-03-14

    申请人： Crossbar, Inc.

    发明人： Harry Yue Gee ,  Steven Patrick Maxwell ,  Natividad Vasquez, Jr. ,  Mark Harold Clark

    IPC分类号： H01L45/00

    CPC分类号： H01L45/1266 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/148 ,  H01L45/1616 ,  H01L45/165 ,  H01L45/1675

    摘要： A memory device comprising a doped conductive polycrystalline layer having an electrically resistive portion, is described herein. By way of example, ion implantation to a subset of the conductive polycrystalline layer can degrade and modify the polycrystalline layer, forming the electrically resistive portion. The electrically resistive portion can include resistive switching properties facilitating digital information storage. Parametric control of the ion implantation can facilitate control over corresponding resistive switching properties of the resistive portion. For example, a projected range or depth of the ion implantation can be controlled, allowing for preferential placement of atoms in the resistive portion, and fine-tuning of a forming voltage of the memory device. As another example, dose and number of atoms implanted, type of atoms or ions that are implanted, the conductive polycrystalline material used, and so forth, can facilitate control over switching characteristics of the memory device.

    摘要翻译： 本文描述了包括具有电阻部分的掺杂导电多晶层的存储器件。 作为示例，离子注入导电多晶层的子集可以降解和修饰多晶层，从而形成电阻部分。 电阻部分可以包括促进数字信息存储的电阻切换特性。 离子注入的参数控制可以有助于控制电阻部分的对应的电阻开关特性。 例如，可以控制离子注入的投影范围或深度，允许优先放置电阻部分中的原子，以及微调存储器件的形成电压。 作为另一示例，注入的原子的剂量和数量，注入的原子或离子的类型，使用的导电多晶材料等等可以有助于对存储器件的开关特性的控制。

    Mitigating damage from a chemical mechanical planarization process
    7.
    发明授权
    Mitigating damage from a chemical mechanical planarization process 有权
    减轻化学机械平面化过程造成的损害

    公开(公告)号：US09437814B1

    公开(公告)日：2016-09-06

    申请号：US14473879

    申请日：2014-08-29

    申请人： Crossbar, Inc.

    发明人： Harry Yue Gee ,  Majid Milani ,  Natividad Vasquez, Jr. ,  Steven Patrick Maxwell ,  Sundar Narayanan

    IPC分类号： H01L21/332 ,  H01L45/00

    CPC分类号： H01L45/16 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145

    摘要： During fabrication of a two-terminal memory device, a terminal (e.g., bottom terminal) can be formed. After formation of the terminal, a chemical mechanical planarization (CMP) process can be applied that, depending on the composition of the terminal, can cause damage that affect operating characteristics of the finished memory device or cell. In some embodiments, such damage can be removed by one or more post-CMP processes. In some embodiments, such damage can be mitigated so as to prevent the damage from occurring at all, by, e.g., forming a sacrificial layer atop the terminal prior to performing the CMP process. Thus, the sacrificial layer can operate to protect the terminal from damage resulting from the CMP process, with the remainder of the sacrificial layer being removed prior to completing the fabrication of the two-terminal memory device.

    摘要翻译： 在制造双端存储器件期间，可以形成端子（例如，底端）。 在端子形成之后，可以应用化学机械平面化（CMP）工艺，根据端子的组成，可以引起影响成品存储器件或电池的工作特性的损坏。 在一些实施例中，可以通过一个或多个后CMP工艺来去除这种损伤。 在一些实施例中，可以减轻这种损害，以便防止在完成CMP过程之前通过例如在端子顶部形成牺牲层来完全发生损坏。 因此，牺牲层可以操作以保护端子免受由CMP工艺引起的损伤，在完成两端存储器件的制造之前牺牲层的其余部分被去除。

    Electrode structure for a non-volatile memory device and method
    8.
    发明授权
    Electrode structure for a non-volatile memory device and method 有权
    用于非易失性存储器件和方法的电极结构

    公开(公告)号：US09312483B2

    公开(公告)日：2016-04-12

    申请号：US13625817

    申请日：2012-09-24

    申请人： Crossbar, Inc.

    发明人： Steven Patrick Maxwell

    IPC分类号： H01L29/02 ,  H01L45/00

    CPC分类号： H01L45/148 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1616 ,  H01L45/1675

    摘要： A method of forming a resistive switching device includes forming a wiring structure over a first dielectric and substrate, forming a junction layer over the wiring structure, forming a resistive switching layer over the junction layer, forming an active metal over the resistive switching layer, forming a tungsten layer over the active metal, forming a barrier layer over the tungsten, depositing a mask over the barrier layer, etching the barrier layer to form a hard mask, etching the junction layer, the resistive switching layer, the active metal layer, and the adhesion layer using the hard mask to form a stack of material, while the adhesion layer maintains adhesion between the barrier layer and the active metal and while side walls of the stack of material have reduced contaminants and have reduced gap regions between the barrier layer and the resistive switching layer.

    摘要翻译： 形成电阻性开关器件的方法包括在第一电介质和衬底上形成布线结构，在布线结构之上形成结层，在结层上形成电阻开关层，在电阻开关层上形成有源金属，形成 在所述活性金属上形成钨层，在所述钨上形成阻挡层，在所述阻挡层上沉积掩模，蚀刻所述阻挡层以形成硬掩模，蚀刻所述接合层，所述电阻开关层，所述活性金属层和 使用硬掩模的粘合层形成一堆材料，同时粘合层保持阻挡层和活性金属之间的粘合性，并且当堆叠材料的侧壁具有减少的污染物并且在阻挡层和 电阻式开关层。

    Sub-oxide interface layer for two-terminal memory
    9.
    发明授权
    Sub-oxide interface layer for two-terminal memory 有权
    二氧化硅接口层用于双端存储器

    公开(公告)号：US09166163B2

    公开(公告)日：2015-10-20

    申请号：US14027045

    申请日：2013-09-13

    申请人： Crossbar, Inc.

    发明人： Harry Yue Gee ,  Mark Harold Clark ,  Steven Patrick Maxwell ,  Sung Hyun Jo ,  Natividad Vasquez, Jr.

    IPC分类号： G11C11/00 ,  H01L45/00

    CPC分类号： H01L45/085 ,  H01L27/2436 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/1608 ,  H01L45/1633

    摘要： Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichimetric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiOX, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide.

    摘要翻译： 本文描述了提供双端存储器件的制造，构造和/或组装。 双端存储器件可以包括具有硅轴承层，界面层和活性金属层的有源区。 可以创建界面层，其包括可以是具有聚集化学式SiO x的多个硅和/或氧化硅层的组合的非重质亚氧化物，其中X可以是大于零且小于2的非整数 亚氧化物可以以各种方式产生，包括与生长亚氧化物，沉积亚氧化物或将现有薄膜转化为亚氧化物相关的各种技术。