公开(公告)号：US11455450B1

公开(公告)日：2022-09-27

申请号：US17337937

申请日：2021-06-03

Applicant: Cadence Design Systems, Inc.

Inventor： Sushobhit Singh ,  Arvind Nembili Veeravalli ,  Naresh Kumar ,  Beenish ,  Mahesh Diwakar Sadhankar ,  Ankit Sethi

IPC: G06F30/30 ,  G06F30/3315 ,  G06F30/31 ,  G06F119/06 ,  G06F119/12 ,  G06F111/02

Abstract: Embodiments include herein are directed towards a method for dynamic voltage and frequency scaling (DVFS) based timing signoff associated with an electronic design environment. Embodiments may include receiving, using a processor, an electronic design and specifying, via a graphical user interface, a voltage sweep for each power net associated with the electronic design. Embodiments may further include specifying, via the graphical user interface, at least one voltage sweep to be excluded from analysis. Embodiments may also include automatically generating DVFS configurations based upon, at least in part, the voltage sweep for each power net and the at least one voltage sweep to be excluded from analysis.