公开(公告)号：US11455450B1

公开(公告)日：2022-09-27

申请号：US17337937

申请日：2021-06-03

Applicant: Cadence Design Systems, Inc.

Inventor： Sushobhit Singh ,  Arvind Nembili Veeravalli ,  Naresh Kumar ,  Beenish ,  Mahesh Diwakar Sadhankar ,  Ankit Sethi

IPC: G06F30/30 ,  G06F30/3315 ,  G06F30/31 ,  G06F119/06 ,  G06F119/12 ,  G06F111/02

Abstract: Embodiments include herein are directed towards a method for dynamic voltage and frequency scaling (DVFS) based timing signoff associated with an electronic design environment. Embodiments may include receiving, using a processor, an electronic design and specifying, via a graphical user interface, a voltage sweep for each power net associated with the electronic design. Embodiments may further include specifying, via the graphical user interface, at least one voltage sweep to be excluded from analysis. Embodiments may also include automatically generating DVFS configurations based upon, at least in part, the voltage sweep for each power net and the at least one voltage sweep to be excluded from analysis.

公开(公告)号：US10114920B1

公开(公告)日：2018-10-30

申请号：US15197142

申请日：2016-06-29

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Umesh Gupta ,  Shashank Tripathi ,  Naresh Kumar ,  Arvind Nembili Veeravalli ,  Prashant Sethia ,  Ritika Govila

IPC: G06F17/50

Abstract: A netlist of a multiple voltage circuit design having a plurality of power domains is established, then inter-power domain (IPD) paths traversing the circuit design are identified, according to whether they traverse multi-supply elements, or are clock paths capturing such a path. The netlist is then pruned to disable or remove cells or stages not traversed by an IPD path. A timing analyzer conducts a multi-domain timing analysis of the IPD timing paths in the pruned IPD netlist. Thereby, the circuit design is thoroughly tested according to the applicable ranges of voltage conditions without excessive runtime.

公开(公告)号：US09881123B1

公开(公告)日：2018-01-30

申请号：US15198635

申请日：2016-06-30

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Ratnakar Goyal ,  Manuj Verma ,  Igor Keller ,  Arvind Nembili Veeravalli

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5031 ,  G06F2217/82

Abstract: A method and system are provided for timing analysis of an electronic circuit design. A timing graph defines a plurality of timing paths through different subsections of the electronic circuit design. A timing window is defined for each of the nodes included in a timing path. At least one preliminary round of a predetermined signal integrity analysis is executed on the circuit design based on the timing windows to identify at least one pair of crosstalk-coupled victim and aggressor nodes. Each victim node's timing window is adaptively adjusted according to a predetermined timing property thereof. At least one primary round of the predetermined signal integrity analysis is executed on the electronic circuit design based in part on this adaptively adjusted timing window for each victim node to generate a delay, which is annotated to the timing graph. A predetermined static timing analysis is executed based on the delay-annotated timing graph.