公开(公告)号：US12007440B1

公开(公告)日：2024-06-11

申请号：US17847421

申请日：2022-06-23

Applicant: Cadence Design Systems, Inc.

Inventor： Puneet Arora ,  Subhasish Mukherjee ,  Sarthak Singhal ,  Christos Papameletis ,  Brian Foutz ,  Krishna V Chakravadhanula ,  Ankit Bandejia ,  Norman Card

IPC: G01R31/3185 ,  G01R31/317 ,  G06F11/267 ,  G06F30/333 ,  G11C29/32

CPC classification number: G01R31/318536 ,  G01R31/318547 ,  G01R31/31704 ,  G01R31/3185 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318583 ,  G06F11/267 ,  G06F30/333 ,  G11C29/32 ,  G11C2029/3202

Abstract: This disclosure relates scan chain stitching. In one example, scan chain elements from a scan chain element space can be received for a scan chain partition. The scan chain elements can be grouped based on scan chain element grouping criteria to form scan chain groups. Scan chain data identifying a number of scan chains for the scan chain partition can be received. The scan chains can be scan chain balanced across the scan chain groups to assign each scan chain to one of the scan chain groups. The scan chain elements associated with each scan chain of the scan chains can be scan chain element balanced. Scan chain elements for each associated scan chain can be connected to form a scan chain data test path during a generation of scan chain circuitry in response to the scan chain element balancing.