公开(公告)号：US09640280B1

公开(公告)日：2017-05-02

申请号：US14930316

申请日：2015-11-02

Applicant: Cadence Design Systems, Inc.

Inventor： Puneet Arora ,  Navneet Kaushik ,  Steven Lee Gregor ,  Norman Card

IPC: G01R31/317 ,  G11C29/38 ,  G01R31/3177 ,  G11C29/10 ,  G11C29/12 ,  G06F17/50

CPC classification number: G11C29/38 ,  G01R31/3177 ,  G06F17/5081 ,  G06F2217/14 ,  G11C29/10 ,  G11C29/12

Abstract: Aspects of the present disclosure involve insertion of power domain aware memory testing logic into integrated circuit designs to enable efficient testing of the memories embedded therein. In example embodiments, each power domain of the integrated circuit, and the memories included therein, are associated with dedicated test data register (TDR) set and instruction set. Each instruction set causes memory test logic circuitry in the integrated circuit to test the memories included in the corresponding power domain in parallel. Once testing of memories within a particular power domain is over, the test circuitry tests memories belonging to another power domain in parallel, and so on.

公开(公告)号：US10699795B1

公开(公告)日：2020-06-30

申请号：US16020083

申请日：2018-06-27

Applicant: Cadence Design Systems, Inc.

Inventor： Norman Card ,  Steven Lee Gregor

IPC: G11C29/00 ,  G11C29/12 ,  G11C29/38 ,  G11C29/18 ,  G06F30/327 ,  G11C29/04

Abstract: A method for identifying a physical memory(ies) associated with a logical memory(ies) in a memory design can include (a) receiving a generic netlist for the memory design, (b) generating a test mode for the memory using the generic netlist, (c) determining the logical memory(ies); (d) performing a simulation on the test mode for the logical memory(ies); and (e) identifying the physical memory(ies) by tracing chip selects for the physical memory(ies) to the logical memory(ies). The identifying the physical memory(ies) may further include identifying which chip selects are active. The identifying the physical memory(ies) can further include tracing an address and a data pin(s) for the logical memory(ies) in the simulation. The identifying the physical memory(ies) can further include determining an address and a data pin(s) for the logical memory(ies) in the simulation.

公开(公告)号：US10095822B1

公开(公告)日：2018-10-09

申请号：US15376403

申请日：2016-12-12

Applicant: Cadence Design Systems, Inc.

Inventor： Navneet Kaushik ,  Puneet Arora ,  Steven Lee Gregor ,  Norman Card

IPC: G06F17/50 ,  G11C29/12

Abstract: In one aspect, electronic design automation systems, methods, and non-transitory computer readable media are presented for adding a memory built-in self-test (MBIST) logic at register transfer level (RTL) or at netlist level into an integrated circuit (IC) design. In some embodiments, the MBIST logic is coupled to a physical memory module via a logical boundary of an intermediate level module that contains the physical memory module. The MBIST logic helps to keep intact integrity of the intermediate level module, making it more likely to meet any specified performance of the intermediate level module and reduce area overhead.

公开(公告)号：US12007440B1

公开(公告)日：2024-06-11

申请号：US17847421

申请日：2022-06-23

Applicant: Cadence Design Systems, Inc.

Inventor： Puneet Arora ,  Subhasish Mukherjee ,  Sarthak Singhal ,  Christos Papameletis ,  Brian Foutz ,  Krishna V Chakravadhanula ,  Ankit Bandejia ,  Norman Card

IPC: G01R31/3185 ,  G01R31/317 ,  G06F11/267 ,  G06F30/333 ,  G11C29/32

CPC classification number: G01R31/318536 ,  G01R31/318547 ,  G01R31/31704 ,  G01R31/3185 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318583 ,  G06F11/267 ,  G06F30/333 ,  G11C29/32 ,  G11C2029/3202

Abstract: This disclosure relates scan chain stitching. In one example, scan chain elements from a scan chain element space can be received for a scan chain partition. The scan chain elements can be grouped based on scan chain element grouping criteria to form scan chain groups. Scan chain data identifying a number of scan chains for the scan chain partition can be received. The scan chains can be scan chain balanced across the scan chain groups to assign each scan chain to one of the scan chain groups. The scan chain elements associated with each scan chain of the scan chains can be scan chain element balanced. Scan chain elements for each associated scan chain can be connected to form a scan chain data test path during a generation of scan chain circuitry in response to the scan chain element balancing.