公开(公告)号：US10783299B1

公开(公告)日：2020-09-22

申请号：US15936999

申请日：2018-03-27

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Puneet Arora ,  Norman Robert Card

IPC: G06F30/00 ,  G06F30/3312 ,  G06F111/20 ,  G06F119/12

Abstract: An exemplary system, method, and computer-accessible medium may be provided, which may include, for example, receiving a design a memory including a plurality MBIST logic paths and a plurality of non-MBIST logic paths, determining particular non-MBIST logic path(s) of the non-MBIST logic paths to deactivate, and deactivating only the particular non-MBIST logic path(s). The particular non-MBIST logic path(s) may be deactivated using a clock signal. A simulation on the memory may be performed while the particular non-MBIST logic path(s) may be deactivated. The particular non-MBIST logic path(s) may be reactivated after the simulation has been performed. The deactivating the particular non-MBIST logic path(s) may include forcing all flip flops in the particular non-MBIST logic path(s) to a known state.

公开(公告)号：US10593419B1

公开(公告)日：2020-03-17

申请号：US15894046

申请日：2018-02-12

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Puneet Arora ,  Norman Robert Card

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/44 ,  G11C29/36

Abstract: Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a sequence iterator unit including a diagnostics analysis unit that monitors and reports on the failing read count associated with the tested memory. Embodiments further provide for a bit fail map report that is generated based on the failing read count.

公开(公告)号：US11971818B1

公开(公告)日：2024-04-30

申请号：US17863985

申请日：2022-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Steven L. Gregor ,  Puneet Arora

IPC: G06F12/08 ,  G11C29/44 ,  G11C29/48

CPC classification number: G06F12/08 ,  G11C29/44 ,  G06F2212/202 ,  G11C29/48

Abstract: A memory view generator evaluates a Liberty file characterizing an NVM module to generate a memory view file for the NVM module. The memory view file includes a port alias identifying ports of the NVM module. The port alias for a set of ports of the NVM module characterizes a type of port in the set of ports. The memory view file includes a port action identifying ports of the NVM module that have a static value and a port access identifying ports of the NVM module that have a dynamic value. The memory view file has an address limit characterizing a number of words in the NVM module and an address partition characterizing address bits and data bits. The memory view file includes a read delay that defines a number of clock cycles needed to hold an address bus stable after a strobe port transitions to an inactive state.

公开(公告)号：US10395747B1

公开(公告)日：2019-08-27

申请号：US15642004

申请日：2017-07-05

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Puneet Arora ,  Norman Robert Card

IPC: G11C29/00 ,  G11C29/14 ,  G06F17/50

Abstract: An exemplary system, method, and computer-accessible medium for modifying a memory unit(s) may be provided, which may include, for example, determining a location of a first memory built-in self-test (MBIST) logic(s) in the memory unit(s), removing the first MBIST logic(s) from the memory unit(s), and inserting a second MBIST logic(s) into the memory unit(s) at the location. The second MBIST logic(s) may be based on the first MBIST logic(s). The second MBIST logic(s) may be generated, which may be performed by modifying the first MBIST logic(s). The first MBIST logic(s) may be modified based on a modification(s) to a register transfer level (RTL) list associated with the memory unit(s). A pattern control file or a Test Data Register mapping file may be modified based on the modification to the first MBIST logic(s).

公开(公告)号：US09640280B1

公开(公告)日：2017-05-02

申请号：US14930316

申请日：2015-11-02

Applicant: Cadence Design Systems, Inc.

Inventor： Puneet Arora ,  Navneet Kaushik ,  Steven Lee Gregor ,  Norman Card

IPC: G01R31/317 ,  G11C29/38 ,  G01R31/3177 ,  G11C29/10 ,  G11C29/12 ,  G06F17/50

CPC classification number: G11C29/38 ,  G01R31/3177 ,  G06F17/5081 ,  G06F2217/14 ,  G11C29/10 ,  G11C29/12

Abstract: Aspects of the present disclosure involve insertion of power domain aware memory testing logic into integrated circuit designs to enable efficient testing of the memories embedded therein. In example embodiments, each power domain of the integrated circuit, and the memories included therein, are associated with dedicated test data register (TDR) set and instruction set. Each instruction set causes memory test logic circuitry in the integrated circuit to test the memories included in the corresponding power domain in parallel. Once testing of memories within a particular power domain is over, the test circuitry tests memories belonging to another power domain in parallel, and so on.

公开(公告)号：US10319459B1

公开(公告)日：2019-06-11

申请号：US15636332

申请日：2017-06-28

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Puneet Arora ,  Norman Robert Card

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/36 ,  G01R31/317

Abstract: An exemplary memory arrangement can be provided, which can include, for example, a memory(ies), and an algorithmic memory unit(s) (AMU) coupled to the memory(ies), wherein the AMU includes a programmed testplan algorithm(s) configured to test the memory(ies). The AMU(s) can further include a hardwired testplan(s) configured to test the memory(ies). A Joint Test Action Group (“JTAG”) controller may be coupled to the AMU(s), which can be configured to access logic of the programmed testplan algorithm(s). A direct access controller (DAC) can be coupled to the AMU(s), which can be configured to access internal nodes in the AMU(s). The DAC can be configured to activate the programmed testplan algorithm(s) using a minimally direct access pin interface in the AMU(s).

公开(公告)号：US09865362B1

公开(公告)日：2018-01-09

申请号：US15019504

申请日：2016-02-09

Applicant: Cadence Design Systems, Inc.

Inventor： Puneet Arora ,  Steven Lee Gregor ,  Norman Robert Card ,  Navneet Kaushik

IPC: G11C29/00 ,  G11C29/42 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/02 ,  G11C29/44

Abstract: Method and apparatus for testing the memory components of an integrated Circuit (IC) using a routing logic and a built-in design for test (DFT) hardware processing device. Based on input provided from an interface controller to the IC, the IC is tested according to one of at least two modes. In a first mode, the built-in DFT hardware processing device executes a test that checks for faults in the physical memory of the IC. In a second mode, the built-in DFT hardware processing device executes a test that checks for faults in the error correction logic of the IC. By using the same routing logic and built-in DFT hardware processing device, tests of the memory components according to the first and second mode can be executed on an automatic and serial basis, even after the manufacture of the IC.

公开(公告)号：US12007440B1

公开(公告)日：2024-06-11

申请号：US17847421

申请日：2022-06-23

Applicant: Cadence Design Systems, Inc.

Inventor： Puneet Arora ,  Subhasish Mukherjee ,  Sarthak Singhal ,  Christos Papameletis ,  Brian Foutz ,  Krishna V Chakravadhanula ,  Ankit Bandejia ,  Norman Card

IPC: G01R31/3185 ,  G01R31/317 ,  G06F11/267 ,  G06F30/333 ,  G11C29/32

CPC classification number: G01R31/318536 ,  G01R31/318547 ,  G01R31/31704 ,  G01R31/3185 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318583 ,  G06F11/267 ,  G06F30/333 ,  G11C29/32 ,  G11C2029/3202

Abstract: This disclosure relates scan chain stitching. In one example, scan chain elements from a scan chain element space can be received for a scan chain partition. The scan chain elements can be grouped based on scan chain element grouping criteria to form scan chain groups. Scan chain data identifying a number of scan chains for the scan chain partition can be received. The scan chains can be scan chain balanced across the scan chain groups to assign each scan chain to one of the scan chain groups. The scan chain elements associated with each scan chain of the scan chains can be scan chain element balanced. Scan chain elements for each associated scan chain can be connected to form a scan chain data test path during a generation of scan chain circuitry in response to the scan chain element balancing.

公开(公告)号：US11966633B1

公开(公告)日：2024-04-23

申请号：US17864135

申请日：2022-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Steven L. Gregor ,  Puneet Arora

IPC: G06F17/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: An NVM algorithm generator that evaluates a Liberty file characterizing an NVM module and a memory view of the NVM module that identifies ports and associated operations of the NVM module to generate a control algorithm. The control algorithm includes a read algorithm that includes an order of operations for assigning values to ports of the NVM module to assert a read condition of a strobe port, executing a memory read on the NVM module and setting values to the ports on the NVM module to assert a complement of a program condition. The control algorithm also includes a program algorithm that includes an order of operations for assigning values to ports of the NVM module to assert the program condition of the strobe port, executing a memory write and setting values to the ports on the NVM module to assert the complement of the program condition.

公开(公告)号：US10482989B1

公开(公告)日：2019-11-19

申请号：US15903916

申请日：2018-02-23

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Puneet Arora ,  Norman Robert Card

IPC: G11C29/38 ,  G11C29/44

Abstract: Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a two-pass diagnostic test of the target memory, wherein, in the first pass, a data compare unit provides clock cycle values associated with detected mis-compares to a tester, and, in the second pass, the data compare unit extracts data vectors associated with the clock cycle values. Embodiments further provide for a bit fail map report that is generated based on the extracted data vectors.