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公开(公告)号：US10389368B1
公开(公告)日：2019-08-20
申请号：US15943491
申请日：2018-04-02
Applicant: Cadence Design Systems, Inc.
Inventor： Fuyue Wang , Ling Chen , Thomas Evan Wilson , Jianyun Zhang , Eric Harris Naviasky
Abstract: Aspects of the present disclosure include a dual path phase locked loop (PLL) circuit with a switched capacitor filter topology along with systems, method, devices, and other circuits related thereto. The dual path PLL circuit includes an integral path and a proportional path. Both the integral path and proportional path include a charge pump and a loop filter. The outputs of a phase frequency detector (PFD) are sent to both charge pumps. The output of the integral path charge pump is connected to a capacitor, and the voltage on capacitor is used as the integral path control voltage for a voltage-controlled oscillator (VCO). A switched capacitor network is connected to the output of the proportional path charge pump and used to generate the proportional path control voltage for the VCO. Together, the two control voltages dictate the VCO's output frequency.
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公开(公告)号：US10345845B1
公开(公告)日：2019-07-09
申请号：US15943499
申请日：2018-04-02
Applicant: Cadence Design Systems, Inc.
Inventor： Ling Chen , Fuyue Wang , Thomas Evan Wilson , Jianyun Zhang , Eric Harris Naviasky
Abstract: Aspects of the present disclosure include systems, methods, devices, and circuits for fast settling of a bias node. Consistent with some embodiments, a bias circuit may include a successive-approximation-register-analog-to-digital converter (SAR-ADC) based settling loop configured to perform a fast settling process for a heavily loaded bias node. The SAR-ADC based loop performs a SAR-ADC process that includes measuring a reference signal to determine a number of cells in a capacitor array that are involved in a charge sharing process while simultaneously completing the settling process for the bias node.
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公开(公告)号：US10161974B1
公开(公告)日：2018-12-25
申请号：US15943487
申请日：2018-04-02
Applicant: Cadence Design Systems, Inc.
Inventor： Ling Chen , Fuyue Wang , Thomas Evan Wilson , Jianyun Zhang , Eric Harris Naviasky
Abstract: Aspects of the present disclosure include a frequency-to-current (F2I) circuit and systems, methods, devices, and other circuits related thereto. The F2I circuit is implemented with a delta-modulator-based control loop to settle and maintain an operating point on a bias node. The control loop provides an integral of an output of a comparator, and the comparator compares it to a self-built voltage reference. Upon powering on the circuit, an integrator in the control loop starts to integrate the charge on both a bias voltage and an internal voltage to provide a settling process for the internal voltage to approximate the reference voltage and for the bias voltage to approximate a predetermined operating point of the bias node. After the circuit has settled, the comparator's output charge toggles and the internal voltage and bias voltage become sawtooth-like waveforms at the reference voltage and operating points, respectively.
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