公开(公告)号：US10482989B1

公开(公告)日：2019-11-19

申请号：US15903916

申请日：2018-02-23

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Puneet Arora ,  Norman Robert Card

IPC: G11C29/38 ,  G11C29/44

Abstract: Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a two-pass diagnostic test of the target memory, wherein, in the first pass, a data compare unit provides clock cycle values associated with detected mis-compares to a tester, and, in the second pass, the data compare unit extracts data vectors associated with the clock cycle values. Embodiments further provide for a bit fail map report that is generated based on the extracted data vectors.

公开(公告)号：US10395747B1

公开(公告)日：2019-08-27

申请号：US15642004

申请日：2017-07-05

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Puneet Arora ,  Norman Robert Card

IPC: G11C29/00 ,  G11C29/14 ,  G06F17/50

Abstract: An exemplary system, method, and computer-accessible medium for modifying a memory unit(s) may be provided, which may include, for example, determining a location of a first memory built-in self-test (MBIST) logic(s) in the memory unit(s), removing the first MBIST logic(s) from the memory unit(s), and inserting a second MBIST logic(s) into the memory unit(s) at the location. The second MBIST logic(s) may be based on the first MBIST logic(s). The second MBIST logic(s) may be generated, which may be performed by modifying the first MBIST logic(s). The first MBIST logic(s) may be modified based on a modification(s) to a register transfer level (RTL) list associated with the memory unit(s). A pattern control file or a Test Data Register mapping file may be modified based on the modification to the first MBIST logic(s).

公开(公告)号：US10319459B1

公开(公告)日：2019-06-11

申请号：US15636332

申请日：2017-06-28

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Puneet Arora ,  Norman Robert Card

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/36 ,  G01R31/317

Abstract: An exemplary memory arrangement can be provided, which can include, for example, a memory(ies), and an algorithmic memory unit(s) (AMU) coupled to the memory(ies), wherein the AMU includes a programmed testplan algorithm(s) configured to test the memory(ies). The AMU(s) can further include a hardwired testplan(s) configured to test the memory(ies). A Joint Test Action Group (“JTAG”) controller may be coupled to the AMU(s), which can be configured to access logic of the programmed testplan algorithm(s). A direct access controller (DAC) can be coupled to the AMU(s), which can be configured to access internal nodes in the AMU(s). The DAC can be configured to activate the programmed testplan algorithm(s) using a minimally direct access pin interface in the AMU(s).

公开(公告)号：US09865362B1

公开(公告)日：2018-01-09

申请号：US15019504

申请日：2016-02-09

Applicant: Cadence Design Systems, Inc.

Inventor： Puneet Arora ,  Steven Lee Gregor ,  Norman Robert Card ,  Navneet Kaushik

IPC: G11C29/00 ,  G11C29/42 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/02 ,  G11C29/44

Abstract: Method and apparatus for testing the memory components of an integrated Circuit (IC) using a routing logic and a built-in design for test (DFT) hardware processing device. Based on input provided from an interface controller to the IC, the IC is tested according to one of at least two modes. In a first mode, the built-in DFT hardware processing device executes a test that checks for faults in the physical memory of the IC. In a second mode, the built-in DFT hardware processing device executes a test that checks for faults in the error correction logic of the IC. By using the same routing logic and built-in DFT hardware processing device, tests of the memory components according to the first and second mode can be executed on an automatic and serial basis, even after the manufacture of the IC.

公开(公告)号：US10387599B1

公开(公告)日：2019-08-20

申请号：US15587032

申请日：2017-05-04

Applicant: Cadence Design Systems, Inc.

Inventor： Puneet Arora ,  Steven Lee Gregor ,  Norman Robert Card

IPC: G06F17/50 ,  G11C29/12 ,  G01R31/3187 ,  G06F11/27

Abstract: Computer system for programmable built-in self-test (PMBIST) insertion into system-on-chip designs comprising one or more memories, including at least one processor and computer-executable instructions that cause the system to determine a PMBIST configuration based on one or more test configuration files; generate one or more package files based on the PMBIST configuration; insert PMBIST hardware into the SoC design based on the package files and characteristics of the memories; suspend PMBIST hardware insertion after an event related to the package files; and resume PMBIST hardware insertion after receiving one or more updated package files. In some embodiments, the package files are independent of vendor-specific memory models. In some embodiments, the package files comprise a plurality of data structures. Exemplary methods and computer-readable media can also be provided embodying one or more procedures the system is configured to perform.

公开(公告)号：US10007489B1

公开(公告)日：2018-06-26

申请号：US15286295

申请日：2016-10-05

Applicant: Cadence Design Systems, Inc.

Inventor： Puneet Arora ,  Steven Lee Gregor ,  Norman Robert Card

IPC: G06F9/44 ,  G06F8/30 ,  G06F3/06 ,  G06F11/36

Abstract: A system and method automatically determines the physical memories inside a core or macro and their association with logical memories and their enabling signals. An integrated circuit (IC) source file that describes an integrated circuit in a hardware description language is received. The IC source file includes macros corresponding to memory. For each macro, a physical description file corresponding to the macro is generated. The description includes how the macro corresponds to the physical memory, associations of physical memories with the logical memory, enabling conditions, and data needed to test the memory.

公开(公告)号：US10783299B1

公开(公告)日：2020-09-22

申请号：US15936999

申请日：2018-03-27

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Puneet Arora ,  Norman Robert Card

IPC: G06F30/00 ,  G06F30/3312 ,  G06F111/20 ,  G06F119/12

Abstract: An exemplary system, method, and computer-accessible medium may be provided, which may include, for example, receiving a design a memory including a plurality MBIST logic paths and a plurality of non-MBIST logic paths, determining particular non-MBIST logic path(s) of the non-MBIST logic paths to deactivate, and deactivating only the particular non-MBIST logic path(s). The particular non-MBIST logic path(s) may be deactivated using a clock signal. A simulation on the memory may be performed while the particular non-MBIST logic path(s) may be deactivated. The particular non-MBIST logic path(s) may be reactivated after the simulation has been performed. The deactivating the particular non-MBIST logic path(s) may include forcing all flip flops in the particular non-MBIST logic path(s) to a known state.

公开(公告)号：US10593419B1

公开(公告)日：2020-03-17

申请号：US15894046

申请日：2018-02-12

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Puneet Arora ,  Norman Robert Card

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/44 ,  G11C29/36

Abstract: Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a sequence iterator unit including a diagnostics analysis unit that monitors and reports on the failing read count associated with the tested memory. Embodiments further provide for a bit fail map report that is generated based on the failing read count.

公开(公告)号：US10541043B1

公开(公告)日：2020-01-21

申请号：US15421158

申请日：2017-01-31

Applicant: Cadence Design Systems, Inc.

Inventor： Carl Alexander Wisnesky, II ,  Patrick Wayne Gallagher ,  Steven Lee Gregor ,  Norman Robert Card

IPC: G11C29/44 ,  G11C29/12 ,  G06F11/25

Abstract: Embodiments relate generally to a scalable, modularized mechanism which allows for storing programmable data streams on chip and provides repeatable on-demand issuances of data streams to one or more targeted instruments. In some embodiments, multiple data streams are grouped into data stream schedules to perform a series of programmable operations on demand. In these and other embodiments, data stream schedules can be reused and further grouped into data stream plans that can be executed in any order upon request or are hard-coded in a specific order.

公开(公告)号：US10387598B1

公开(公告)日：2019-08-20

申请号：US15703503

申请日：2017-09-13

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Norman Robert Card

IPC: G06F17/50

Abstract: An exemplary bitmap file can be provided, which can include, for example, a map of a cell array structure of a memory(ies), a plurality of memory values superimposed on the cell array structure based on a simulated testing of the memory(ies). The memory values may be values being written to the memory(ies) while the memory(ies) is being tested. The memory values may be values in a test pattern(s) being used to test the memory(ies). Each cell in the cell array structure can have a particular memory value superimposed thereon. A cell(s) in the cell array structure may be highlighted, which may correspond to an incorrect memory value.