公开(公告)号：US11777491B1

公开(公告)日：2023-10-03

申请号：US17896915

申请日：2022-08-26

Applicant: Cadence Design Systems, Inc.

Inventor： Riju Biswas

IPC: H03K17/56 ,  H04L27/01

CPC classification number: H03K17/56 ,  H04L27/01

Abstract: Various embodiments provide for a continuous time linear equalizer (CTLE) that includes an active inductor, which can be included in a receiver portion of a circuit. For some embodiments, the CTLE in combination with the active inductor can implement a signal transfer function comprising at least two zeros and two poles.

公开(公告)号：US11979264B1

公开(公告)日：2024-05-07

申请号：US18092756

申请日：2023-01-03

Applicant: Cadence Design Systems, Inc.

Inventor： Riju Biswas ,  Abhishek Shrivastava

IPC: H04L25/03

CPC classification number: H04L25/03878 ,  H04L25/03057

Abstract: Methods and systems are provided for processing a signal over a serial link. The methods and systems receive, by an adjustable filter, a serial input signal, the adjustable filter configured to set a corner frequency of a channel response and a gain of the channel response, the adjustable filter adding a zero to the channel response before to a pole of the serial input signal. The methods and systems selectively apply, by a bandwidth booster component, compensation to signal attenuation of the serial input signal in a first mode of operation and of one or more test signals in a second mode of operation of a serial link receiver. The methods and systems generate, by one or more continuous time linear equalizers configured to receive on an output of the bandwidth booster, one or more output signals of the receiver based on an output signal from the bandwidth booster component.

公开(公告)号：US11757458B1

公开(公告)日：2023-09-12

申请号：US17692246

申请日：2022-03-11

Applicant: Cadence Design Systems, Inc.

Inventor： Vineeth Anavangot ,  Riju Biswas

IPC: H03D3/24 ,  H03L7/18 ,  H03L7/099 ,  H04L7/033

CPC classification number: H03L7/1806 ,  H03L7/099 ,  H04L7/033

Abstract: In some examples, a digital phase-locked loop (PLL) circuit can include a switch to provide a reference input signal having a first frequency in response to an output signal having a second frequency that is greater than the first frequency. The circuit includes a comparator to provide a series of bits based on the reference input signal and a comparator reference signal, and proportional accumulator circuits to provide during respective different time intervals a proportional bit based on a respective bit of the series of bits and a previously outputted proportional bit by a respective proportional accumulator circuit. The circuit includes shift registers to shift the respective bit of the series to provide a shifted bit during the respective different time intervals, and a cancellation circuit to output a filtered proportional bit during the respective different time intervals based on the proportional bit and the shifted bit.