公开(公告)号：US11757458B1

公开(公告)日：2023-09-12

申请号：US17692246

申请日：2022-03-11

Applicant: Cadence Design Systems, Inc.

Inventor： Vineeth Anavangot ,  Riju Biswas

IPC: H03D3/24 ,  H03L7/18 ,  H03L7/099 ,  H04L7/033

CPC classification number: H03L7/1806 ,  H03L7/099 ,  H04L7/033

Abstract: In some examples, a digital phase-locked loop (PLL) circuit can include a switch to provide a reference input signal having a first frequency in response to an output signal having a second frequency that is greater than the first frequency. The circuit includes a comparator to provide a series of bits based on the reference input signal and a comparator reference signal, and proportional accumulator circuits to provide during respective different time intervals a proportional bit based on a respective bit of the series of bits and a previously outputted proportional bit by a respective proportional accumulator circuit. The circuit includes shift registers to shift the respective bit of the series to provide a shifted bit during the respective different time intervals, and a cancellation circuit to output a filtered proportional bit during the respective different time intervals based on the proportional bit and the shifted bit.

公开(公告)号：US11271782B1

公开(公告)日：2022-03-08

申请号：US17013109

申请日：2020-09-04

Applicant: Cadence Design Systems, Inc.

Inventor： Vineeth Anavangot ,  Maitri Misra ,  Rajesh Cheeranthodi

IPC: H04L25/03 ,  H03K17/687

Abstract: In some examples, a receiver can include a sampler circuit that can be configured to process a data input signal corresponding to a current bit received at a receiver based on a capacitive weighted signal to compensate for distortion effects that a previously received bit at the receiver has on the data input signal. The receiver can include a capacitive coupling feedback circuit that can be configured to generate the capacitive weighted signal corresponding to a weighted detected bit of the previously received bit based on a capacitance of a subset of capacitors of a plurality of capacitors of the feedback circuit. The capacitive coupling feedback circuit can be configured to selectively control a number of capacitors of the plurality of capacitors that are connected in parallel corresponding to the subset of capacitors to control an amount of weight applied to the detected bit to generate the capacitive weighted signal.

公开(公告)号：US10171270B1

公开(公告)日：2019-01-01

申请号：US15849288

申请日：2017-12-20

Applicant: Cadence Design Systems, Inc.

Inventor： Satish Anand Verkila ,  Vineeth Anavangot ,  Anil Kumar Ankam

IPC: H04L25/03 ,  H04L1/00

Abstract: Various embodiments provide for correcting pre-cursor intersymbol interference (ISI) and post-cursor ISI in a data signal received over a channel. More particularly, some embodiments correct pre-cursor ISI and post-cursor ISI using decision feedback equalization (DFE).