公开(公告)号：US10558780B1

公开(公告)日：2020-02-11

申请号：US15721845

申请日：2017-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Singh Kukal ,  Arnold Jean Marie Gustave Ginetti ,  Jagdish Lohani ,  Harmohan Singh ,  Ritabrata Bhattacharya ,  Balvinder Singh

IPC: G06F17/50 ,  H05K3/00

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing schematic driven extracted views for an electronic design. These techniques identify a schematic circuit component design represented by a schematic symbol from a schematic design and identifying layout device information from a layout of the electronic design. An extracted view is generated anew or updated from an existing extracted view at least by placing and interconnecting a symbol in the schematic design based at least in part upon the layout device information. The electronic design may be further updated based in part or in whole upon results of performing one or more analyses on the extracted view.

公开(公告)号：US09934354B1

公开(公告)日：2018-04-03

申请号：US15205593

申请日：2016-07-08

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Singh Kukal ,  Balvinder Singh ,  Steven R. Durrill ,  Arnold Ginetti ,  Vikrant Khanna ,  Abhishek Dabral ,  Madhur Sharma ,  Nikhil Gupta ,  Ritabrata Bhattacharya

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5077 ,  G06F2217/40 ,  G06F2217/74

Abstract: Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.