公开(公告)号：US10285276B1

公开(公告)日：2019-05-07

申请号：US15275230

申请日：2016-09-23

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Kukal ,  Arnold Ginetti ,  Steven R. Durrill ,  Abhay Agarwal ,  Vikas Kohli ,  Tyler Lockman

IPC: G06F11/22 ,  G06F17/50 ,  H05K3/00

Abstract: A method is provided that includes receiving shape data specifying a shape of an electromagnetic (EM) structure in a circuit layout and transferring the shape data to a schematic cell representation based on a logic function of the EM structure and package technology layers of the circuit layout. The method includes placing a symbol for the EM structure in the schematic cell representation, associating the shape data and a model path with a cell parameter in the symbol, mapping the shape data to the package technology layers, and specifying pins in the schematic cell representation according to the shape data. Further, the method includes verifying ports for the EM structure and placing the EM structure in a package layout for a printed circuit board (PCB). A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.

公开(公告)号：US09934354B1

公开(公告)日：2018-04-03

申请号：US15205593

申请日：2016-07-08

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Singh Kukal ,  Balvinder Singh ,  Steven R. Durrill ,  Arnold Ginetti ,  Vikrant Khanna ,  Abhishek Dabral ,  Madhur Sharma ,  Nikhil Gupta ,  Ritabrata Bhattacharya

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5077 ,  G06F2217/40 ,  G06F2217/74

Abstract: Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.

公开(公告)号：US09881119B1

公开(公告)日：2018-01-30

申请号：US14754535

申请日：2015-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Singh Kukal ,  Steven R. Durrill ,  Arnold Ginetti

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036

Abstract: Disclosed are techniques for generating a parasitic-aware simulation schematic across multiple design fabrics. These techniques identify a first extracted model from existing extracted models for a first circuit component design in a first layout in a first design fabric of an electronic design that spans across multiple design fabrics. These techniques further generate a simulation schematic by inserting the first extracted model into the simulation schematic. In addition, a simulation may be performed with the simulation schematic to generate simulation results. Schematic models, if existing, may also be used to revise the simulation schematic. For circuit component designs corresponding to no extract models or schematic models, one or more extracted models placeable in the simulation schematic may also be constructed to update the simulation schematic.