公开(公告)号：US09785738B1

公开(公告)日：2017-10-10

申请号：US14972809

申请日：2015-12-17

Applicant: Cadence Design Systems, Inc.

Inventor： Charles Jay Alpert ,  Zhuo Li ,  Wing Kai Chow ,  Wen-Hao Liu ,  Derong Liu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077

Abstract: The present disclosure relates to a system and method for evaluating spanning trees. Embodiments may include receiving, using at least one processor, a spanning tree including one or more sinks coupled by one or more edges. Embodiments may further include receiving a user-selected floating parameter. Embodiments may also include interchanging the one or more edges of the spanning tree based upon, at least in part, the user-selected floating parameter.

公开(公告)号：US10755024B1

公开(公告)日：2020-08-25

申请号：US16148182

申请日：2018-10-01

Applicant: Cadence Design Systems, Inc.

Inventor： Wing Kai Chow ,  Mehmet Yildiz ,  Zhuo Li

IPC: G06F30/394 ,  G06F30/327 ,  G06F111/20 ,  G06F111/04

Abstract: The present disclosure relates to a system and method for routing in an electronic circuit design. Embodiments may include providing, using a processor, a hierarchical electronic design having a plurality of partitions, at least one routing blockage, a source pin location, and one or more sink pin locations. Embodiments may also include generating a routing wire network configured to connect the source pin location and the one or more sink pin locations to create one or more segments, wherein generating the routing wire network includes creating two or more feed-through ports at one or more of the plurality of partitions. Embodiments may further include applying a maze-routing approach to each of the one or more segments of the routing wire network to form a routed net associated with the hierarchical electronic design.