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1.发明授权Concurrent network of reduction processors for executing programs stored as treelike graphs employing variable-free applicative language codes 失效用于执行存储为使用可变免费应用语言代码的树状图的程序的还原处理器并发网络
公开(公告)号：US4502118A
公开(公告)日：1985-02-26
申请号：US530066
申请日：1983-09-07
IPC分类号： G06F9/44 , G06F15/173 , G06F15/80 , G06F13/00 , G06F15/00
CPC分类号： G06F9/4436 , G06F15/17343 , G06F15/8023
摘要： This disclosure relates to a network of reduction processors for the evaluation of one or more functions which are stored in memory in the form of a series of nodes of a treelike graph where the nodes implement a variable-free applicative language. The respective function operators are reduced through a progressive series of transformations or substitutions until a result is obtained. During the reduction process, the processor transfers nodes to and from memory and performs various operations as required on those nodes. The processor can also create new nodes in memory and delete unused ones.
摘要翻译： 本公开涉及用于评估以节点实现无变量应用语言的一系列节点形式存储在存储器中的一个或多个功能的简化处理器网络。 各个功能运算符通过渐进的一系列变换或替代来减少，直到获得结果为止。 在还原过程中，处理器将节点传送到存储器并从存储器传送节点，并根据需要执行各种操作。 处理器还可以在内存中创建新节点并删除未使用的节点。
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2.发明授权Reduction processor for executing programs stored as treelike graphs employing variable-free applicative language codes 失效还原处理器用于执行存储为使用可变免费应用语言代码的三维图形的程序
公开(公告)号：US4447875A
公开(公告)日：1984-05-08
申请号：US281064
申请日：1981-07-07
CPC分类号： G06F9/4436
摘要： This disclosure relates to a reduction processor for the evaluation of one or more functions which are stored in memory in the form of a series of nodes of a treelike graph where the nodes implement a variable-free applicative language. The respective function operators are reduced through a progressive series of transformations or substitutions until a result is obtained. During the reduction process, the processor transfers nodes to and from memory and performs various operations as required on those nodes. The processor can also create new nodes in memory and delete unused ones.
摘要翻译： 本公开涉及一种用于评估以节点实现无变量应用语言的一系列节点形式存储在存储器中的一个或多个功能的简化处理器。 各个功能运算符通过渐进的一系列变换或替代来减少，直到获得结果为止。 在还原过程中，处理器将节点传送到存储器并从存储器传送节点，并根据需要执行各种操作。 处理器还可以在内存中创建新节点并删除未使用的节点。
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公开(公告)号：US4498133A
公开(公告)日：1985-02-05
申请号：US329423
申请日：1981-12-10
CPC分类号： G06F13/14 , G06F13/4022 , G06F15/80
摘要： Disclosed is a selector switch for use in forming an asynchronous network of concurrent processors where the selector switch receives a message from one input port and transmits it to one of two output ports. A path through the network which has been established can be cleared should it become apparent that that particular path has become locked in due to a malfunction of a component in one of the nodes or switches in the network.
摘要翻译： 公开了一种用于形成并行处理器的异步网络的选择器开关，其中选择器开关从一个输入端口接收消息并将其发送到两个输出端口之一。 如果由于网络中的一个节点或交换机中的组件的故障而使特定路径变得被锁定，则可以清除已经建立的通过网络的路径。
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公开(公告)号：US4488151A
公开(公告)日：1984-12-11
申请号：US329424
申请日：1981-12-10
IPC分类号： B61B12/10 , B61B12/00 , B66D1/50 , G06F13/14 , G06F13/40 , G06F15/16 , G06F15/173 , G06F15/177 , G06F15/80 , H04Q9/00 , H04J3/02
CPC分类号： G06F15/17375 , B61B12/00 , B61B12/007 , G06F13/14 , G06F13/4022 , G06F15/80
摘要： Disclosed is an arbiter switch for use in forming an asynchronous network of concurrent processors where the arbiter switch receives a message from one of two input ports and transmits it to its output port. A path through the network which has been established can be cleared should it become apparent that particular path has become locked in due to a malfunction of a component in one of the nodes or switches in the network.
摘要翻译： 公开了一种用于形成并发处理器的异步网络的仲裁器交换机，其中仲裁器交换机从两个输入端口之一接收消息并将其发送到其输出端口。 如果由于网络中的一个节点或交换机中的组件的故障而特定路径已经被锁定，则可以清除已经建立的通过网络的路径。
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5.发明授权Parallel register transfer mechanism for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes 失效用于还原处理器的并行寄存器传送机制，评估使用无变量应用语言代码存储为二进制定向图的程序
公开(公告)号：US4654780A
公开(公告)日：1987-03-31
申请号：US617531
申请日：1984-06-05
CPC分类号： G06F9/30032 , G06F9/30072 , G06F9/30141 , G06F9/4436
摘要： A parallel register-transfer mechanism has been disclosed above for use in the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expression is reduced through a series of transformations until a result is obtained. A register file is provided with several crossbar networks interconnecting the various registers in the file for simultaneous transfer of their contents.
摘要翻译： 以上已经公开了一种并行寄存器传送机制，用于评估存储为二进制有向图的无变量应用语言的表达式。 通过一系列转换来减少表达，直到获得结果。 寄存器文件提供有多个互连网络，将文件中的各种寄存器互连，以便同时传送其内容。
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6.发明授权System memory for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes 失效用于还原处理器的系统存储器评估使用无变量应用语言代码存储为二进制定向图的程序
公开(公告)号：US4616315A
公开(公告)日：1986-10-07
申请号：US690842
申请日：1985-01-11
CPC分类号： G06F9/4436
摘要： A system memory for a reduction processor which evaluates programs stored as binary graphs employing variable-free applicative language codes. These graphs are made up of nodes, each of which exists in memory and contains as its most significant bit a mark bit which when set indicates that the node is being used in a graph and when reset indicates that the node or storage location is available for future use by the processor. In order to accommodate the scanning of a number of storage locations in parallel, the system memory is divided into a node memory and the mark bit memory so that the mark bits for a number of sequential storage locations can be examined in parallel to determine which node locations are free for use by the graph manager.
摘要翻译： 一种用于还原处理器的系统存储器，其使用无变量的应用语言代码评估存储为二进制图形的程序。 这些图形由节点组成，每个节点都存在于存储器中，并且包含最高有效位的标记位，当设置指示节点正在图形中使用时，并且当复位指示节点或存储位置可用于 未来由处理器使用。 为了平行地适应多个存储位置的扫描，系统存储器被划分为节点存储器和标记位存储器，以便可并行地检查多个顺序存储位置的标记位以确定哪个节点 位置可由图表管理员自由使用。
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7.发明授权Condition concentrator and control store for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes 失效用于缩减处理器的条件集中器和控制存储器评估使用无变量应用语言代码存储为二进制定向图的程序
公开(公告)号：US4615003A
公开(公告)日：1986-09-30
申请号：US617532
申请日：1984-06-05
申请人： Gary L. Logsdon , Mark R. Scheevel
发明人： Gary L. Logsdon , Mark R. Scheevel
CPC分类号： G06F9/264 , G06F9/30072 , G06F9/30094 , G06F9/4436
摘要： Parallel register-transfer mechanism and control section have been disclosed above for use in a reduction processor for the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expressions are reduced through a series of transformations until a result is obtained.
摘要翻译： 以上已经公开了用于还原处理器中的平行寄存器传送机制和控制部分，用于评估存储为二进制定向图的无变量应用语言的表达式。 通过一系列转换来减少表达式，直到获得结果。
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8.发明授权Allocator for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes 失效用于还原处理器的分配器评估使用无变量应用语言代码存储为二进制定向图的程序
公开(公告)号：US4598361A
公开(公告)日：1986-07-01
申请号：US690846
申请日：1985-01-11
CPC分类号： G06F9/4436
摘要： An allocator for a reduction processor which evaluates programs stored as binary graphs employing variable-free applicative language codes. These graphs are made up of nodes, each of which exists in memory and contains as its most significant bit a mark bit which when set indicates that the node is being used in a graph and when reset indicates that the node or storage location is available for future use by the processor. The allocator scans selected groups of storage locations in parallel to see if there are any unused storage locations and then places the addresses of those unused storage locations in a queue for use by the processor.
摘要翻译： 用于还原处理器的分配器，其使用无变量的应用语言代码评估存储为二进制图的程序。 这些图形由节点组成，每个节点都存在于存储器中，并且包含最高有效位的标记位，当设置指示节点正在图形中使用时，并且当复位指示节点或存储位置可用于 未来由处理器使用。 分配器并行扫描所选择的存储位置组，以查看是否存在任何未使用的存储位置，然后将这些未使用的存储位置的地址放置在队列中以供处理器使用。
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9.发明授权Graph manager for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes 失效用于还原处理器的图管理器评估使用无变量应用语言代码存储为二进制定向图的程序
公开(公告)号：US4644464A
公开(公告)日：1987-02-17
申请号：US617526
申请日：1984-06-05
CPC分类号： G06F9/4436
摘要： A parallel register-transfer mechanism and control section have been disclosed above for use in a reduction process for the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expressions are reduced through a series of transformations until a result is obtained.
摘要翻译： 以上已经公开了一种并行寄存器传送机制和控制部分，用于评估作为二进制定向图存储的无变量应用语言表达式的简化处理。 通过一系列转换来减少表达式，直到获得结果。
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10.发明授权Five port module as a node in an asynchronous speed independent network of concurrent processors 失效五端口模块作为节点在异步速度独立的并发处理器网络中
公开(公告)号：US4482996A
公开(公告)日：1984-11-13
申请号：US414071
申请日：1982-09-02
申请人： Jesse R. Wilson , Gary L. Logsdon
发明人： Jesse R. Wilson , Gary L. Logsdon
IPC分类号： G06F15/177 , G06F15/173 , G06F15/80 , H04J6/00
CPC分类号： G06F15/17375 , G06F15/80
摘要： A five port module as a node in an asynchronous speed independent network of concurrent processors, each port of the module including an input selector switch and an output selector switch such that each selector switch has a plurality of output channels one for each of the output arbiter switches (except the arbiter switch associated with its own port). Each selector switch is adapted to select a particular output channel (arbiter switch) according to the initial bits received in the asynchronous speed independent message. In this manner, the module of the present invention can accommodate up to five simultaneous asynchronous message transmissions without nodal blocking although the average number of simultaneous messages that can be accommodated will be less. The respective arbiter and selector switches are provided with circuitry to respond to a clear signal that resets the corresponding arbiter and selector switches forming a particular transmission path should nodal blocking occur.
摘要翻译： 作为并行处理器的异步速度独立网络中的节点的五端口模块，模块的每个端口包括输入选择器开关和输出选择器开关，使得每个选择器开关具有多个输出通道，用于每个输出仲裁器 交换机（与其自己的端口相关联的仲裁器交换机除外）。 每个选择器开关适于根据在异步速度独立消息中接收到的初始位选择特定的输出通道（仲裁器开关）。 以这种方式，本发明的模块可以容纳多达五个不同节点的同步异步消息传输，尽管可以容纳的同时消息的平均数量将较少。 相应的仲裁器和选择器开关设置有电路，用于响应清除信号，该清除信号复位相应的仲裁器和选择器开关，形成特定传输路径，如果发生节点阻塞。
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