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    Silicon-on-insulator vertical array device trench capacitor DRAM
    1.
    发明授权
    Silicon-on-insulator vertical array device trench capacitor DRAM 有权
    绝缘体上的垂直阵列器件沟槽电容器DRAM

    公开(公告)号：US06566177B1

    公开(公告)日：2003-05-20

    申请号：US09427257

    申请日：1999-10-25

    申请人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

    发明人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

    IPC分类号： H01L2100

    CPC分类号： H01L27/10864 ,  H01L27/1087

    摘要： A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench. A polysilicon capacitor plate is formed in the deep trenches and conductive polysilicon straps are formed in the trenches between the capacitor plates and the SOI sidewalls. Device regions are defined in the wafer and a sidewall gate is formed in the deep trenches. Shallow trenches isolation (STI) is used to isolate and define cells. Bitlines and wordlines are formed on the wafer.

    摘要翻译： 一种绝缘体上硅（SOI）动态随机存取存储器（DRAM）单元及阵列及其制造方法。 存储单元包括通过自对准埋入带连接到垂直存取晶体管的沟槽存储电容器。 掩埋氧化层将SOI层与硅衬底隔离。 沟槽电容器形成在衬底中，并且存取晶体管形成在SOI层的侧壁上。 连接到存储电容器的多晶硅板的多晶硅带提供与存取晶体管的源极的自对准接触。 最初，在晶圆中形成掩埋氧化物层。 深沟槽被蚀刻，最初刚刚通过SOI层和BOX层。 在沟槽中形成保护侧壁。 然后，将深沟槽蚀刻到衬底中。 衬底中的体积被扩大以形成瓶形沟槽。 在深沟槽中形成多晶硅电容器板，并且在电容器板和SOI侧壁之间的沟槽中形成导电多晶硅带。 在晶片中限定器件区域，并且在深沟槽中形成侧壁栅极。 浅沟槽隔离（STI）用于隔离和定义细胞。 在晶片上形成位线和字线。

    Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap
    2.
    发明授权
    Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap 失效
    绝缘体上的垂直阵列DRAM单元，具有自对准埋地带

    公开(公告)号：US06426252B1

    公开(公告)日：2002-07-30

    申请号：US09427256

    申请日：1999-10-25

    申请人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

    发明人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

    IPC分类号： H01L218242

    CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/1203

    摘要： A silicon on insulator (SOI) dynamic random access memory (DRAM) cell, array and method of manufacture. The memory cell includes a vertical access transistor above a trench storage capacitor in a layered wafer. A buried oxide (BOX) layer formed in a silicon wafer isolates an SOI layer from a silicon substrate. Deep trenches are etched through the upper surface SOI layer, the BOX layer and into the substrate. Each trench capacitor is formed in the substrate and, the access transistor is formed on a sidewall of the SOI layer. Recesses are formed in the BOX layer at the SOI layer. A polysilicon strap recessed in the BOX layer connects each polysilicon storage capacitor plate to a self-aligned contact at the source of the access transistor. Dopant is implanted into the wafer to define device regions. Access transistor gates are formed along the SOI layer sidewalls. Shallow trenches are formed and filled with insulating material to isolate cells from adjacent cells. Wordlines and bitlines are formed to complete the memory array.

    摘要翻译： 绝缘体上硅（SOI）动态随机存取存储器（DRAM）单元，阵列和制造方法。 存储单元包括在分层晶片中的沟槽存储电容器上方的垂直存取晶体管。 形成在硅晶片中的掩埋氧化物（BOX）层将SOI层与硅衬底隔离。 深沟槽通过上表面SOI层，BOX层蚀刻并进入衬底。 每个沟槽电容器形成在衬底中，并且存取晶体管形成在SOI层的侧壁上。 在SOI层的BOX层中形成凹部。 凹陷在BOX层中的多晶硅带将每个多晶硅存储电容器板连接到存取晶体管的源极处的自对准接触。 将掺杂剂注入到晶片中以限定器件区域。 存取晶体管栅极沿SOI层侧壁形成。 形成浅沟槽并填充绝缘材料以将细胞与相邻细胞分离。 形成字词和位线以完成内存数组。

    6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI
    6.
    发明授权
    6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI 失效
    6F2沟槽EDRAM单元，具有双门控垂直MOSFET和自对准STI

    公开(公告)号：US06570208B2

    公开(公告)日：2003-05-27

    申请号：US09766013

    申请日：2001-01-18

    申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Gary B. Bronner

    发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Gary B. Bronner

    IPC分类号： H01L218242

    CPC分类号： H01L27/10864 ,  H01L21/823481 ,  H01L21/823487

    摘要： A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substantially eliminates the backgating problem and floating well effects that are typically present in prior art memory cells. A method of fabricating the inventive memory cell is also provided.

    摘要翻译： 提供了包含双门控垂直金属氧化物半导体场效应晶体管（MOSFET）和隔离区域（诸如浅沟槽隔离，STI，与电池的字线和位线自对准的区域）的存储单元。 本发明的存储单元基本上消除了现有技术的存储单元中通常存在的背景问题和漂浮阱效应。 还提供了制造本发明的存储单元的方法。

    Static self-refreshing DRAM structure and operating mode
    7.
    发明授权
    Static self-refreshing DRAM structure and operating mode 失效
    静态自刷新DRAM结构和工作模式

    公开(公告)号：US06501117B1

    公开(公告)日：2002-12-31

    申请号：US10007846

    申请日：2001-11-05

    申请人： Carl J. Radens ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Jack A. Mandelman

    发明人： Carl J. Radens ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Jack A. Mandelman

    IPC分类号： H01L27108

    CPC分类号： H01L27/11 ,  G11C11/404 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10867 ,  H01L29/945

    摘要： A DRAM cell storage capacitor is formed above the bottom of a deep trench (DT) below an FET transistor. The DT has upper, central and lower portions with sidewalls. A capacitor plate electrode, surrounding the lower DT portion that is doped with a first dopant type, is separated by an interface from a well region surrounding the upper and central portions of the DT that are doped with an opposite dopant type. A source/drain region formed at the top of the cell is doped with the first dopant type. A node dielectric layer that covers the sidewalls and bottom of the lower and central portions of the DT is filled with a node electrode of the capacitor, doped with the first dopant type, fills the space inside the node dielectric layer in the lower part of the DT. Above a recessed node dielectric layer a strap region space is filled with a buried-strap conductor. An oxide (TTO) layer is formed over the node electrode and the buried-strap in the DT. A peripheral gate oxide layer, which coats sidewalls of the DT above the TTO, defines a space which is filled with the FET gate electrode. An outdiffusion region, doped with the first dopant type, is formed in the well region near the buried-strap. The cell has a first state and an opposite state of operation. A punch-through device, formed in the well between the outdiffusion region and the interface, provides a self-refreshing punchthrough current in the cell between the well and the plate in the first state of cell operation. A reverse bias junction leakage current occurs in the cell between the buried-strap and the P-well to refresh the opposite state of cell operation.

    摘要翻译： 在FET晶体管下方的深沟槽（DT）的底部形成DRAM单元存储电容器。 DT具有具有侧壁的上部，中部和下部。 围绕掺杂有第一掺杂剂类型的下部DT部分的电容器平板电极通过界面与围绕掺杂有相反掺杂剂类型的DT的上部和中部的阱区隔开。 形成在电池顶部的源极/漏极区掺杂有第一掺杂剂类型。 覆盖DT的下部和中心部分的侧壁和底部的节点电介质层填充有掺杂有第一掺杂剂类型的电容器的节点电极，填充第一掺杂剂类型的下部的节点电介质层内部的空间 DT。 在凹陷节点电介质层上方，带区域空间填充有埋地导体。 在DT上的节点电极和掩埋带上形成氧化物（TTO）层。 在TTO上方覆盖DT的侧壁的外围栅极氧化物层限定了用FET栅电极填充的空间。 在掩埋带附近的阱区中形成掺杂有第一掺杂剂类型的扩散区。 电池具有第一状态和相反的操作状态。 形成在扩散区域和界面之间的井中的穿通装置在电池操作的第一状态下在孔和板之间的电池单元中提供自刷新穿透电流。 在埋层和P阱之间的电池中产生反向偏置结漏电流，以刷新电池操作的相反状态。

    Single sided buried strap
    9.
    发明授权
    Single sided buried strap 失效
    单面埋地带

    公开(公告)号：US06426526B1

    公开(公告)日：2002-07-30

    申请号：US09870068

    申请日：2001-05-30

    申请人： Ramachandra Divakaruni ,  Jack A. Mandelman ,  Gary B. Bronner ,  Carl J. Radens

    发明人： Ramachandra Divakaruni ,  Jack A. Mandelman ,  Gary B. Bronner ,  Carl J. Radens

    IPC分类号： H01L27108

    CPC分类号： H01L27/10864

    摘要： An easily manufactured connecting structure from a node conductor of trench capacitor device is characterized at least in part by the presence of an isolation collar located above the node conductor, at least a portion of the collar having an exterior surface which is substantially conformal with at least a portion of an adjacent wall of the trench, a buried strap region in the trench above the node conductor, the strap region being bounded laterally by the isolation collar except at an opening in the collar. The connecting structure is preferably formed by a method involving clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench.

    摘要翻译： 至少部分地由位于节点导体上方的隔离套管的存在而将来自沟槽电容器装置的节点导体的容易制造的连接结构的特征在于，所述套环的至少一部分具有至少基本上保形的外表面 沟槽的相邻壁的一部分，在节点导体上方的沟槽中的掩埋带区域，除了在套环的开口处之外，带区域被隔离套环侧向限定。 连接结构优选地通过一种方法来形成，该方法包括在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环，同时将隔离套环留在深沟槽的其他表面。

    Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure
    10.
    发明授权
    Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure 失效
    具有垂直MOSFET和埋地位线导体结构的4F2 STC电池的工艺

    公开(公告)号：US06348374B1

    公开(公告)日：2002-02-19

    申请号：US09597887

    申请日：2000-06-19

    申请人： Satish D. Athavale ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

    发明人： Satish D. Athavale ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

    IPC分类号： H01L218242

    CPC分类号： H01L27/10876 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10885

    摘要： A method of forming a vertical transistor. A pad layer is formed over a semiconductor substrate. A trough is formed through the pad layer and in the semiconductor substrate. A bit line is formed buried in the trough. The bit line is enclosed by a dielectric material. A strap is formed extending through the dielectric material to connect the bit line to the semiconductor substrate. The trough is filled above the bit line with a conductor. The conductor is cut along its longitudinal axis such that the conductor remains on one side of the trough. Wordline troughs are formed, substantially orthogonal to the bit line, above the semiconductor substrate. A portion of the conductor is removed under the wordline trough to separate the conductor into separate gate conductors. Wordlines are formed in the wordline trough connected to the separate gate conductors.

    摘要翻译： 一种形成垂直晶体管的方法。 在半导体衬底上形成衬垫层。 通过焊盘层和半导体衬底形成槽。 埋在槽中的位线形成。 位线被电介质材料包围。 形成延伸穿过介电材料的带，以将位线连接到半导体衬底。 槽被填充在位线上方的导体。 导体沿其纵向轴线切割，使得导体保持在槽的一侧。 在半导体衬底之上形成基本上与位线正交的字线槽。 导体的一部分在字线槽下移除，以将导体分离成单独的栅极导体。 字线形成在连接到单独的栅极导体的字线槽中。