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公开(公告)号：US20060202706A1
公开(公告)日：2006-09-14
申请号：US11356713
申请日：2006-02-17
IPC分类号： G01R31/02
CPC分类号： G11C29/1201 , G01R31/31921 , G11C29/40 , G11C29/48 , G11C2029/5602
摘要： In a method for testing an electric circuit comprising circuit subunits, the electric circuit is connected to a test system via a tester channel with a connection unit. The tester channel is connected to the circuit subunits by means of a connecting unit, test signals are generated for the electric circuit and response signals generated by the electric circuit in response to the test signals are evaluated. The test signals and the response signals are interchanged between the circuit subunits by means of at least one compression/decompression unit associated with at least one of the circuit subunits.
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公开(公告)号：US20060120199A1
公开(公告)日：2006-06-08
申请号：US11270025
申请日：2005-11-09
IPC分类号： G11C5/14
CPC分类号： G11C29/12 , G11C29/78 , G11C2029/1208 , G11C2029/4402 , G11C2229/743 , G11C2229/763
摘要： An electronic circuit comprises a volatile memory unit and a non-volatile memory unit which stores a repair information related to the volatile memory unit. The non-volatile and volatile memory units are connected together by a connecting device and are formed as a single electronic module.
摘要翻译： 电子电路包括易失性存储器单元和存储与易失性存储器单元相关的修复信息的非易失性存储器单元。 非易失性和易失性存储器单元通过连接装置连接在一起并形成为单个电子模块。
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公开(公告)号：US07574643B2
公开(公告)日：2009-08-11
申请号：US11356713
申请日：2006-02-17
IPC分类号： G01R31/28
CPC分类号： G11C29/1201 , G01R31/31921 , G11C29/40 , G11C29/48 , G11C2029/5602
摘要： In a method for testing an electric circuit comprising circuit subunits, the electric circuit is connected to a test system via a tester channel with a connection unit. The tester channel is connected to the circuit subunits by means of a connecting unit, test signals are generated for the electric circuit and response signals generated by the electric circuit in response to the test signals are evaluated. The test signals and the response signals are interchanged between the circuit subunits by means of at least one compression/decompression unit associated with at least one of the circuit subunits.
摘要翻译： 在用于测试包括电路子单元的电路的方法中，电路经由具有连接单元的测试器通道连接到测试系统。 测试仪通道通过连接单元连接到电路子单元，产生用于电路的测试信号，并且响应于测试信号对电路产生的响应信号进行评估。 测试信号和响应信号通过与至少一个电路子单元相关联的至少一个压缩/解压缩单元在电路子单元之间互换。
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4.发明申请Electronic test apparatus and method for testing at least one circuit unit 审中-公开用于测试至少一个电路单元的电子测试装置和方法公开(公告)号：US20070101223A1
公开(公告)日：2007-05-03
申请号：US11586370
申请日：2006-10-25
申请人： Christian Chetreanu , Stefan Gollmer , Amir Leber , Roman Mayr
发明人： Christian Chetreanu , Stefan Gollmer , Amir Leber , Roman Mayr
IPC分类号： G01R31/28
CPC分类号： G01R31/31928 , G01R31/31922 , G01R31/31937 , G11C29/48 , G11C29/56 , G11C29/56012 , G11C2029/5602
摘要： An electronic test apparatus for testing at least one circuit unit comprises a clock signal generator for generating a clock signal, a driver device comprising a plurality of driver subunits each generating a phase-shifted driver signal in response to said clock signal, a processing device for processing the phase-shifted driver signals and for comparing actual data being output by at least one circuit unit with desired data generated in the processing device, a connecting device for connecting the processing device to the at least one circuit unit and for transmitting the phase-shifted driver signals, the desired data, and the actual data between the processing device and the at least one circuit unit, and a combinational logic device for combining the phase-shifted driver signals to form a clock combination signal.
摘要翻译： 一种用于测试至少一个电路单元的电子测试装置包括用于产生时钟信号的时钟信号发生器，包括响应于所述时钟信号产生相移驱动器信号的多个驱动器子单元的驱动器装置，用于 处理相移的驱动器信号，并将由至少一个电路单元输出的实际数据与在处理装置中生成的期望数据进行比较;连接装置，用于将处理装置连接到至少一个电路单元， 移位的驱动器信号，期望数据以及处理装置与至少一个电路单元之间的实际数据，以及用于组合相移驱动器信号以形成时钟组合信号的组合逻辑装置。
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