摘要:
In a method of testing a memory device, an output path of the memory device and an input path of the memory device are coupled to each other. A signal is transmitted, controlled by a test pattern, via the output path of the memory device. The signal is received via the input path of the memory device and evaluated.
摘要:
A method for calibrating a test apparatus for parallel testing of a number of semiconductor memories, to a time-critical parameter, in which the components are positioned in batches at predetermined test positions and the parameter is measured. The various test positions give different measurement results since they are not identical. These different measurement results are compensated for by the following steps: The invention provides for a position-specific mean value MPS to be formed from batch parameter measurements at each test position, for a position-independent mean value MPU to be formed for the batch parameter measurements at all the test positions, and for a corrected mean value to be obtained for each test position by adding a correction value &dgr;, which is determined from the difference between the position-specific mean value MPS and the position-independent mean value MPU, to the position-specific mean value MPS.
摘要:
A system and method for testing an integrated circuit is provided. In one embodiment, a method includes comparing the signal level of the output signal of the integrated circuit to the signal level of a reference signal, wherein a comparison signal is output, which has a first or a second value depending on whether the actual signal level of the output signal is above or below the actual signal level of the reference signal; determining the value of the comparison signal at a certain time; evaluating the value of the comparison signal determined at the time by way of a default; and outputting an error signal if the determined value of the comparison signal does not correspond to the default.
摘要:
An electronic test apparatus for testing at least one circuit unit comprises a clock signal generator for generating a clock signal, a driver device comprising a plurality of driver subunits each generating a phase-shifted driver signal in response to said clock signal, a processing device for processing the phase-shifted driver signals and for comparing actual data being output by at least one circuit unit with desired data generated in the processing device, a connecting device for connecting the processing device to the at least one circuit unit and for transmitting the phase-shifted driver signals, the desired data, and the actual data between the processing device and the at least one circuit unit, and a combinational logic device for combining the phase-shifted driver signals to form a clock combination signal.
摘要:
A test apparatus for semiconductor modules. One embodiment provides a test system. The test system includes a handler configured to receive at least one semiconductor module. The test system is equipped with a plurality of different pin cards. The handler has at least two independent groups of test receptacles.
摘要:
A system and method for testing an integrated circuit is provided. In one embodiment, a method includes comparing the signal level of the output signal of the integrated circuit to the signal level of a reference signal, wherein a comparison signal is output, which has a first or a second value depending on whether the actual signal level of the output signal is above or below the actual signal level of the reference signal; determining the value of the comparison signal at a certain time; evaluating the value of the comparison signal determined at the time by way of a default; and outputting an error signal if the determined value of the comparison signal does not correspond to the default.
摘要:
A semi-conductor component test procedure, as well as a system for testing semi-conductor components. The invention relates to a semi-conductor component test procedure, as well as a system for testing semi-conductor components (3a, 3b, 3c, 3d), by means of a first and a second test apparatus (6a, 6b), whereby the first test apparatus (6a) is arranged and installed such that a time-discrete semi-conductor component test is performed by it on a particular semi-conductor component (3a), and whereby the second test apparatus (6a) is arranged and installed such that a separate, time-continuous semi-conductor component test is performed by it on the same semi-conductor component (3a).