公开(公告)号：US06958505B2

公开(公告)日：2005-10-25

申请号：US09955926

申请日：2001-09-18

申请人： Catherine Mallardeau ,  Pascale Mazoyer ,  Marc Piazza

发明人： Catherine Mallardeau ,  Pascale Mazoyer ,  Marc Piazza

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10882 ,  H01L27/10888

摘要： There is provided an integrated circuit having active components including junctions formed in a monocrystalline substrate doped locally, and at least one passive component situated above the active components. The integrated circuit includes a first insulating layer separating the active components and abase of the passive component, and a metal terminal for electrically connecting the passive component with at least one of the active components. The metal terminal is formed in the thickness of the first insulating layer and has a contact surface that projects from the limits of a junction of the one active component. In a preferred embodiment, the passive component is a capacitor. Also provided is a method of fabricating an integrated circuit that includes MOS transistors and an onboard memory plane of DRAM cells in a matrix.

摘要翻译： 提供了一种集成电路，其具有包括局部掺杂的单晶衬底中形成的结的有源部件和位于有源部件上方的至少一个无源部件。 集成电路包括分离有源部件的第一绝缘层和无源部件的放宽，以及用于将无源部件与至少一个有源部件电连接的金属端子。 金属端子形成为第一绝缘层的厚度，并且具有从一个有源部件的接合极限突出的接触表面。 在优选实施例中，无源部件是电容器。 还提供了一种制造集成电路的方法，该集成电路包括MOS晶体管和矩阵中的DRAM单元的板载存储器平面。

公开(公告)号：US07259414B2

公开(公告)日：2007-08-21

申请号：US10486950

申请日：2002-08-14

申请人： Catherine Mallardeau ,  Pascale Mazoyer ,  Marc Piazza

发明人： Catherine Mallardeau ,  Pascale Mazoyer ,  Marc Piazza

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L28/91

摘要： This integrated circuit comprises a capacitor (23) formed above a substrate (1) inside a first cavity in a dielectric and comprising a first electrode, a second electrode, a thin dielectric layer placed between the two electrodes, and a structure (7) for connection to the capacitor.The connection structure is formed at the same level as the capacitor in a second cavity narrower than the first cavity, the said second cavity being completely filled by an extension of at least one of the electrodes of the capacitor.

摘要翻译： 该集成电路包括形成在电介质的第一空腔内部的衬底（1）上方的电容器（23），其包括第一电极，第二电极，设置在两个电极之间的薄介电层，以及用于 连接到电容器。 连接结构形成在与第一空腔更窄的第二空腔中的电容器相同的水平处，所述第二空腔由电容器的至少一个电极的延伸部完全填充。

公开(公告)号：US06908811B2

公开(公告)日：2005-06-21

申请号：US10817468

申请日：2004-04-02

申请人： Marc Piazza ,  Philippe Coronel

发明人： Marc Piazza ,  Philippe Coronel

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10885

摘要： A method for forming in monolithic form a DRAM-type memory, including the steps of forming, on a substrate, parallel strips including a lower insulating layer, a strongly-conductive layer, a single-crystal semiconductor layer, and an upper insulating layer; digging, perpendicularly to the strips, into the upper insulating layer and into a portion of the semiconductor layer, first and second parallel trenches, each first and second trench being shared by neighboring cells; forming, in each first trench, a first conductive line according to the strip width; forming, in each second trench, two second distinct parallel conductive lines, insulated from the peripheral layers; filling the first and second trenches with an insulating material; removing the remaining portions of the upper insulating layer; and depositing a conductive layer.

摘要翻译： 一种用于以单片形式形成DRAM型存储器的方法，包括以下步骤：在衬底上形成包括下绝缘层，强导电层，单晶半导体层和上绝缘层的平行条带; 垂直于条带挖掘到上绝缘层中并进入半导体层的一部分，第一和第二平行沟槽，每个第一和第二沟槽由相邻单元共享; 在每个第一沟槽中，根据条带宽度形成第一导电线; 在每个第二沟槽中形成与外围层绝缘的两个第二不同的平行导线; 用绝缘材料填充第一和第二沟槽; 去除上绝缘层的剩余部分; 并沉积导电层。

公开(公告)号：US06800515B2

公开(公告)日：2004-10-05

申请号：US10304580

申请日：2002-11-26

申请人： Marc Piazza

发明人： Marc Piazza

IPC分类号： H01L21336

CPC分类号： H01L27/10855 ,  H01L21/3144 ,  H01L27/0629 ,  H01L27/10811

摘要： A method for manufacturing DRAM cells in a semiconductor wafer including MOS control transistors and capacitors, the source/drain regions and the gates of the control transistors being covered with a protection layer and with an insulating layer, in which the capacitors are formed at the level of openings formed in the insulating layer which extend to the protection layer covering the gates, and in which first capacitor electrodes are connected to source/drain regions of the control transistors by conductive vias crossing the insulating layer and the protection layer.

摘要翻译： 一种用于在包括MOS控制晶体管和电容器的半导体晶片中制造DRAM单元的方法，控制晶体管的源极/漏极区域和栅极被保护层和绝缘层覆盖，其中电容器形成在该层 在绝缘层中形成的开口，其延伸到覆盖栅极的保护层，并且其中第一电容器电极通过与绝缘层和保护层交叉的导电通孔连接到控制晶体管的源/漏区。

公开(公告)号：US06759304B2

公开(公告)日：2004-07-06

申请号：US10042520

申请日：2002-01-09

申请人： Philippe Coronel ,  Marc Piazza ,  François Leverd

发明人： Philippe Coronel ,  Marc Piazza ,  François Leverd

IPC分类号： H01L2120

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： The invention relates to a DRAM integration method that does away with the alignment margins inherent to the photoetching step of the upper electrode of the capacitance for inserting the bit line contact. The removal of the upper electrode is self-aligned on the lower electrode of the capacitance. This is accomplished by forming a difference in topography at the point where the opening of the upper electrode is to be made, and depositing a non-doped polysilicon layer on the upper electrode. An implantation of dopants is performed on this layer, and the part of the non-doped layer located in the lower part of the zone showing the difference in topography is selectively etched. The remainder of the polysilicon layer and the part of the upper electrode located in the lower layer are also etched.

摘要翻译： 本发明涉及一种DRAM积分方法，其消除了用于插入位线接触的电容的上电极的光刻步骤固有的对准边缘。 上电极的去除在电容的下电极上自对准。 这是通过在要形成上电极的开口的位置处形成不同的形貌并在上电极上沉积非掺杂多晶硅层来实现的。 在该层上进行掺杂剂的注入，并且选择性地蚀刻位于显示区域差异的区域下部的非掺杂层的部分。 多晶硅层的剩余部分和位于下层的上部电极的一部分也被蚀刻。

公开(公告)号：US06740919B2

公开(公告)日：2004-05-25

申请号：US10255392

申请日：2002-09-26

申请人： Marc Piazza ,  Philippe Coronel

发明人： Marc Piazza ,  Philippe Coronel

IPC分类号： H01L27108

CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10885

摘要： A method for forming in monolithic form a DRAM-type memory, including the steps of forming, on a substrate, parallel strips including a lower insulating layer, a strongly-conductive layer, a single-crystal semiconductor layer, and an upper insulating layer; digging, perpendicularly to the strips, into the upper insulating layer and into a portion of the semiconductor layer, first and second parallel trenches, each first and second trench being shared by neighboring cells; forming, in each first trench, a first conductive line according to the strip width; forming, in each second trench, two second distinct parallel conductive lines, insulated from the peripheral layers; filling the first and second trenches with an insulating material; removing the remaining portions of the upper insulating layer; and depositing a conductive layer.

摘要翻译： 一种用于以单片形式形成DRAM型存储器的方法，包括以下步骤：在衬底上形成包括下绝缘层，强导电层，单晶半导体层和上绝缘层的平行条带; 垂直于条带挖掘到上绝缘层中并进入半导体层的一部分，第一和第二平行沟槽，每个第一和第二沟槽由相邻单元共享; 在每个第一沟槽中，根据条带宽度形成第一导电线; 在每个第二沟槽中形成与外围层绝缘的两个第二不同的平行导线; 用绝缘材料填充第一和第二沟槽; 去除上绝缘层的剩余部分; 并沉积导电层。