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    Dynamic adjustment of wordline timing in static random access memory
    2.
    发明授权
    Dynamic adjustment of wordline timing in static random access memory 有权

    公开(公告)号：US11935587B2

    公开(公告)日：2024-03-19

    申请号：US17555501

    申请日：2021-12-19

    申请人： Ceremorphic, Inc.

    发明人： Robert F. Wiser ,  Neelam Surana

    IPC分类号： G11C11/418 ,  G11C8/08 ,  G11C11/419

    CPC分类号： G11C11/418 ,  G11C8/08 ,  G11C11/419

    摘要： A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable wordline signal pulse width which may be reduced sufficiently to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and a nearly error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline signal pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline signal pulse width with an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.

    Address dependent wordline timing in asynchronous static random access memory
    4.
    发明授权
    Address dependent wordline timing in asynchronous static random access memory 有权

    公开(公告)号：US12068024B2

    公开(公告)日：2024-08-20

    申请号：US17734045

    申请日：2022-04-30

    申请人： Ceremorphic, Inc.

    发明人： Jay A. Chesavage ,  Robert Wiser ,  Neelam Surana

    IPC分类号： G11C11/408 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096

    CPC分类号： G11C11/4096 ,  G11C11/4085 ,  G11C11/4093 ,  G11C11/4094

    摘要： A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.