公开(公告)号：US20140040844A1

公开(公告)日：2014-02-06

申请号：US13564751

申请日：2012-08-02

申请人： Chandramouli Visweswariah ,  Eric Fluhr ,  Stephen G. Shuma ,  Debjit Sinha ,  Michael H. Wood

发明人： Chandramouli Visweswariah ,  Eric Fluhr ,  Stephen G. Shuma ,  Debjit Sinha ,  Michael H. Wood

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis to determine timing violations. Each timing violation in its statistical canonical form is examined. In a first aspect of the invention, the canonical failing slack is inspected to determine what type of move is most likely to fix the timing violation taking into account all relevant manufacturing and environmental variations. In a second aspect of the invention, pre-characterized moves such as insertion of delay pad cells are evaluated for their ability to fix the timing violation without triggering timing, and the best move or set of moves is selected.

摘要翻译： 在存在制造和环境变化的情况下执行集成电路的定时关闭的方法。 使用统计静态时序分析来分析起始设计，以确定时序违规。 检查其统计规范形式的每个时间违规。 在本发明的第一方面，检查规范的故障松弛以确定哪种类型的移动最有可能在考虑到所有相关的制造和环境变化的情况下修复定时违规。 在本发明的第二方面中，评估了诸如插入延迟垫单元之类的预先表征的移动能够固定定时违反而不触发定时，并且选择最佳移动或移动集合。

公开(公告)号：US08732642B2

公开(公告)日：2014-05-20

申请号：US13564751

申请日：2012-08-02

申请人： Chandramouli Visweswariah ,  Eric Fluhr ,  Stephen G. Shuma ,  Debjit Sinha ,  Michael H. Wood

发明人： Chandramouli Visweswariah ,  Eric Fluhr ,  Stephen G. Shuma ,  Debjit Sinha ,  Michael H. Wood

IPC分类号： G06F9/455

CPC分类号： G06F17/5031

摘要： Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis to determine timing violations. Each timing violation in its statistical canonical form is examined. In a first aspect of the invention, the canonical failing slack is inspected to determine what type of move is most likely to fix the timing violation taking into account all relevant manufacturing and environmental variations. In a second aspect of the invention, pre-characterized moves such as insertion of delay pad cells are evaluated for their ability to fix the timing violation without triggering timing, and the best move or set of moves is selected.

摘要翻译： 在存在制造和环境变化的情况下执行集成电路的定时关闭的方法。 使用统计静态时序分析来分析起始设计，以确定时序违规。 检查其统计规范形式的每个时间违规。 在本发明的第一方面，检查规范的故障松弛以确定哪种类型的移动最有可能在考虑到所有相关的制造和环境变化的情况下修复定时违规。 在本发明的第二方面中，评估了诸如插入延迟垫单元之类的预先表征的移动能够固定定时违反而不触发定时，并且选择最佳移动或移动集合。

公开(公告)号：US20080091922A1

公开(公告)日：2008-04-17

申请号：US11953637

申请日：2007-12-10

申请人： Eric Fluhr ,  Bradly Frey ,  John Griswell ,  Hung Le ,  Cathy May ,  Francis O'Connell ,  Edward Silha ,  Albert Williams

发明人： Eric Fluhr ,  Bradly Frey ,  John Griswell ,  Hung Le ,  Cathy May ,  Francis O'Connell ,  Edward Silha ,  Albert Williams

IPC分类号： G06F9/38

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

公开(公告)号：US20060179239A1

公开(公告)日：2006-08-10

申请号：US11054889

申请日：2005-02-10

申请人： Eric Fluhr ,  Bradly Frey ,  John Griswell ,  Hung Le ,  Cathy May ,  Francis O'Connell ,  Edward Silha ,  Albert Williams

发明人： Eric Fluhr ,  Bradly Frey ,  John Griswell ,  Hung Le ,  Cathy May ,  Francis O'Connell ,  Edward Silha ,  Albert Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

摘要翻译： 在微处理器中预取数据的方法包括基于包括当前并发数据流的数量和与并发数据流相关联的数据消耗速率的预取因子来识别与进程相关联的数据流并确定与数据流相关联的深度。 数据预取请求被分配与数据流以反映确定的数据流的深度。 分配数据预取请求可以包括为当前被引用的高速缓存行分配多个高速缓存行的预取请求，其中高速缓存行的数量等于所确定的深度。 该方法可以响应于确定与数据流相关联的深度，配置预取硬件以反映所识别的数据流的确定的深度。 由处理器执行的指令中的预取控制位控制预取硬件配置。

公开(公告)号：US20060198297A1

公开(公告)日：2006-09-07

申请号：US11054287

申请日：2005-02-09

申请人： Andrew Bianchi ,  Eric Fluhr ,  Masood Khan ,  Michael Hyeok Lee ,  Edelmar Seewann

发明人： Andrew Bianchi ,  Eric Fluhr ,  Masood Khan ,  Michael Hyeok Lee ,  Edelmar Seewann

IPC分类号： H04L12/26

CPC分类号： G06F13/4018 ,  G11C7/1006

摘要： A method and apparatus for using a 2:1 MUX to control read access, data bypass, and page size bypass in a memory array. The mechanism of the present invention reduces the 3:1 MUX normally required to manage these three functions to a 2:1 MUX.

摘要翻译： 一种使用2：1 MUX来控制存储器阵列中的读访问，数据旁路和页大小旁路的方法和装置。 本发明的机制将通常需要的3：1 MUX将这三个功能管理到2：1 MUX。

公开(公告)号：US20060184734A1

公开(公告)日：2006-08-17

申请号：US11055828

申请日：2005-02-11

申请人： Eric Fluhr ,  Sheldon Levenstein

发明人： Eric Fluhr ,  Sheldon Levenstein

IPC分类号： G06F12/00

CPC分类号： G06F12/04 ,  G06F12/0846 ,  G06F12/0886

摘要： A technique for improving access times when accessing memory, such as when accessing data from cache. By a unique manipulation and usage of a specified memory address in combination with the cache's internal organization, the address range required by the requested data can be covered by one odd and one even segment of the cache, where the odd segment is always at the base address created by the summation of the source operands and set to the odd segment, and the even address is created by summation of the source operands plus an offset value equivalent to the size of the cache line. This structural regularity is used to efficiently generate both the even and odd addresses in parallel to retrieve the desired data.

摘要翻译： 一种用于在访问内存时改进访问时间的技术，例如从缓存访问数据时。 通过与高速缓存的内部组织结合使用指定的存储器地址的独特操作和使用，所请求的数据所需的地址范围可以由高速缓存的一个奇数和一个偶数段覆盖，其中奇数段总是在基地 地址由源操作数的总和创建并设置为奇数段，偶数地址是通过源操作数的加法加上与缓存行大小相等的偏移值来创建的。 这种结构规律性用于有效地同时产生偶数和奇数地址以检索所需数据。

公开(公告)号：US20080010433A1

公开(公告)日：2008-01-10

申请号：US11837241

申请日：2007-08-10

申请人： Eric Fluhr ,  Sheldon Levenstein

发明人： Eric Fluhr ,  Sheldon Levenstein

IPC分类号： G06F9/34

CPC分类号： G06F12/04 ,  G06F12/0846 ,  G06F12/0886

摘要： A technique for improving access times when accessing memory, such as when accessing data from cache. By a unique manipulation and usage of a specified memory address in combination with the cache's internal organization, the address range required by the requested data can be covered by one odd and one even segment of the cache, where the odd segment is always at the base address created by the summation of the source operands and set to the odd segment, and the even address is created by summation of the source operands plus an offset value equivalent to the size of the cache line. This structural regularity is used to efficiently generate both the even and odd addresses in parallel to retrieve the desired data.

摘要翻译： 一种用于在访问内存时改进访问时间的技术，例如从缓存访问数据时。 通过与高速缓存的内部组织结合使用指定的存储器地址的独特操作和使用，所请求的数据所需的地址范围可以由高速缓存的一个奇数和一个偶数段覆盖，其中奇数段总是在基地 地址由源操作数的总和创建并设置为奇数段，偶数地址是通过源操作数的加法加上与缓存行大小相等的偏移值来创建的。 这种结构规律性用于有效地同时产生偶数和奇数地址以检索所需数据。

公开(公告)号：US20060181909A1

公开(公告)日：2006-08-17

申请号：US11055803

申请日：2005-02-11

申请人： Joaquin Hinojosa ,  Eric Fluhr ,  Michael Lee ,  Jose Paredes ,  Ed Seewann

发明人： Joaquin Hinojosa ,  Eric Fluhr ,  Michael Lee ,  Jose Paredes ,  Ed Seewann

IPC分类号： G11C15/00

CPC分类号： G06F12/1027 ,  G06F2212/652 ,  G11C15/00

摘要： A CAM system is disclosed in which requests for address translation are provided as input search data to a dynamic compare bitline generator. The dynamic compare bitline generator also receives a compare mask and applies the compare mask to associated input search data bits on a per bit basis. The mask contains information that specifies a selected page size and a selected logic mode that can be applied to a compare array in which the specified search is conducted. The compare array is coupled to a data array to which the compare array indicates a result of the search.

摘要翻译： 公开了一种CAM系统，其中将地址转换请求作为输入搜索数据提供给动态比较位线发生器。 动态比较位线发生器还接收比较掩码，并以比特的形式将比较掩码应用于相关的输入搜索数据位。 掩码包含指定所选页面大小的信息和可应用于进行指定搜索的比较数组的选定逻辑模式。 比较数组耦合到比较数组指示搜索结果的数据阵列。