公开(公告)号：US20050167728A1

公开(公告)日：2005-08-04

申请号：US10769101

申请日：2004-01-29

申请人： Chandrasekharan Kothandaraman ,  Danny Shum

发明人： Chandrasekharan Kothandaraman ,  Danny Shum

IPC分类号： G11C16/04 ,  G11C29/00 ,  H01L21/336 ,  H01L23/525 ,  H01L27/115 ,  H01L29/788 ,  H01L29/76

CPC分类号： H01L27/115 ,  G11C16/0433 ,  G11C29/789 ,  G11C2216/10 ,  H01L23/5256 ,  H01L29/66825 ,  H01L29/7885 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically programmable transistor fuse having a double-gate arrangement disposed in a single layer of polysilicon in which a first gate is disposed overlapping a portion of a source region and a second gate is insulated from the first gate and disposed overlapping a portion of a drain region. The first gate includes a terminal for receiving an externally applied control signal and the second gate is capacitively couple to the drain region in which a coupling device is included for increasing the capacitive coupling of the second gate and the drain region for enabling reduction in fuse programming voltage.

摘要翻译： 具有设置在单层多晶硅中的双栅极布置的电可编程晶体管熔丝，其中第一栅极被布置成与源极区域的一部分重叠并且第二栅极与第一栅极绝缘，并且与漏极的一部分重叠 地区。 第一栅极包括用于接收外部施加的控制信号的端子，并且第二栅极电容耦合到其中包括耦合装置的漏极区域，以增加第二栅极和漏极区域的电容耦合，以便能够减少熔丝编程 电压。

公开(公告)号：US07075127B2

公开(公告)日：2006-07-11

申请号：US10769101

申请日：2004-01-29

申请人： Chandrasekharan Kothandaraman ,  Danny Shum

发明人： Chandrasekharan Kothandaraman ,  Danny Shum

IPC分类号： H01L27/105

CPC分类号： H01L27/115 ,  G11C16/0433 ,  G11C29/789 ,  G11C2216/10 ,  H01L23/5256 ,  H01L29/66825 ,  H01L29/7885 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically programmable transistor fuse having a double-gate arrangement disposed in a single layer of polysilicon in which a first gate is disposed overlapping a portion of a source region and a second gate is insulated from the first gate and disposed overlapping a portion of a drain region. The first gate includes a terminal for receiving an externally applied control signal and the second gate is capacitively couple to the drain region in which a coupling device is included for increasing the capacitive coupling of the second gate and the drain region for enabling reduction in fuse programming voltage.

摘要翻译： 具有设置在单层多晶硅中的双栅极布置的电可编程晶体管熔丝，其中第一栅极被布置成与源极区域的一部分重叠并且第二栅极与第一栅极绝缘，并且与漏极的一部分重叠 地区。 第一栅极包括用于接收外部施加的控制信号的端子，并且第二栅极电容耦合到其中包括耦合装置的漏极区域，以增加第二栅极和漏极区域的电容耦合，以便能够减少熔丝编程 电压。

公开(公告)号：US20070057307A1

公开(公告)日：2007-03-15

申请号：US11223235

申请日：2005-09-09

申请人： Danny Shum ,  Armin Tilke ,  Jiang Yan

发明人： Danny Shum ,  Armin Tilke ,  Jiang Yan

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices.

摘要翻译： 公开了闪存器件结构及其制造方法。 闪存器件是在绝缘体上硅（SOI）衬底上制造的。 使用浅沟槽隔离（STI）区域和SOI衬底的掩埋氧化物层来隔离相邻器件。 制造方法需要更少的光刻掩模，并且可以在独立的闪存器件，嵌入式闪存器件以及片上系统（SoC）闪存器件中实现。

公开(公告)号：US08389357B2

公开(公告)日：2013-03-05

申请号：US13052728

申请日：2011-03-21

申请人： Ronald Kakoschke ,  Thomas Nirschl ,  Danny Shum ,  Klaus Schrüfer

发明人： Ronald Kakoschke ,  Thomas Nirschl ,  Danny Shum ,  Klaus Schrüfer

IPC分类号： H01L21/336

CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L29/8616

摘要： A method of fabricating a memory device in a semiconductor substrate, the device having a memory array having a plurality of memory cell transistors arranged in rows and columns. The method includes forming a plurality of tunneling field effect transistors, forming a first well of the second doping type, forming a second well of the first doping type surrounding the first well, forming a first word line connected to a first row of memory cell transistors, forming a first bit line to control a voltage of doped drain regions of tunneling field effect transistors of a first column of memory cell transistors, and forming a second bit line parallel to the first bit line.

摘要翻译： 一种在半导体衬底中制造存储器件的方法，该器件具有存储器阵列，该存储器阵列具有排列成行和列的多个存储单元晶体管。 该方法包括形成多个隧穿场效应晶体管，形成第二掺杂类型的第一阱，形成围绕第一阱的第一掺杂类型的第二阱，形成连接到第一行存储单元晶体管的第一字线 形成第一位线，以控制第一列存储单元晶体管的隧穿场效应晶体管的掺杂漏极区的电压，以及形成与第一位线平行的第二位线。

公开(公告)号：US20080026520A1

公开(公告)日：2008-01-31

申请号：US11868001

申请日：2007-10-05

申请人： Jiang Yan ,  Chun-Yung Sung ,  Danny Shum ,  Alois Gutmann

发明人： Jiang Yan ,  Chun-Yung Sung ,  Danny Shum ,  Alois Gutmann

IPC分类号： H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/78687

摘要： In a method of forming a semiconductor device, a wafer includes a first semiconductor region of a first crystal orientation and a second semiconductor region of a second crystal orientation. Insulating material is formed over the wafer. A first portion of the insulating material is removed to expose the first semiconductor region and a second portion of the insulating material is removed to expose the second semiconductor region. Semiconductor material of the first crystal orientation is epitaxially grown over the exposed first semiconductor region and semiconductor material of the second crystal orientation is epitaxially grown over the exposed second semiconductor region

摘要翻译： 在形成半导体器件的方法中，晶片包括第一晶体取向的第一半导体区域和第二晶体取向的第二半导体区域。 在晶片上形成绝缘材料。 除去绝缘材料的第一部分以暴露第一半导体区域，并且去除绝缘材料的第二部分以暴露第二半导体区域。 在暴露的第一半导体区域上外延生长第一晶体取向的半导体材料，并且在暴露的第二半导体区域上外延生长第二晶体取向的半导体材料

公开(公告)号：US07190022B2

公开(公告)日：2007-03-13

申请号：US11081886

申请日：2005-03-16

申请人： Danny Shum ,  Georg Tempel ,  Ronald Kakoschke

发明人： Danny Shum ,  Georg Tempel ,  Ronald Kakoschke

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546

摘要： An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.

摘要翻译： 集成电路具有高电压区域，逻辑区域和存储器阵列，用于在包括线性，逻辑和存储器件的芯片上形成系统。 存储器阵列具有布置在三阱结构中的浮置栅极晶体管，其高位漏极位线13基本上与掩埋源极线14垂直对准。 存储器阵列将列可以形成为电荷泵电容器的深沟槽46分离。

公开(公告)号：US07176088B2

公开(公告)日：2007-02-13

申请号：US10513163

申请日：2004-03-18

申请人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

发明人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/66833

摘要： The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.

摘要翻译： 本发明涉及一种具有表面位线（DLx）和掩埋位线（SLx）的位线结构，埋入位线（SLx）形成在具有沟槽绝缘层（6）的沟槽中，并与掺杂 通过覆盖连接层（12）和沟槽的上部部分区域中的自对准端子层（13）与其接触的区域（10）。

公开(公告)号：US5283203A

公开(公告)日：1994-02-01

申请号：US843705

申请日：1992-02-28

申请人： Manzur Gill ,  Danny Shum

发明人： Manzur Gill ,  Danny Shum

IPC分类号： H01L21/28 ,  H01L21/74 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/092 ,  H01L27/115 ,  H01L21/265

CPC分类号： H01L21/743 ,  H01L23/485 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S148/018 ,  Y10S148/133

摘要： A method for making a NMOS self-aligned contact in CMOS circuits without an extra mask is described. The maskless contact technique makes use of the fact that the blanket N-type implant, self-aligned to exposed field-oxide edge, will not change the P+ diffusion to N-type. The net P+ concentration in the contact region is reduced slightly but does not degrade the PMOS device performance.

摘要翻译： 描述了在没有额外掩模的CMOS电路中制造NMOS自对准接触的方法。 无掩模接触技术利用以下事实：自对准到曝光的场氧化物边缘的覆盖N型注入不会将P +扩散改变为N型。 接触区域中的净P +浓度略有减小，但不会降低PMOS器件性能。

公开(公告)号：US08288813B2

公开(公告)日：2012-10-16

申请号：US10918335

申请日：2004-08-13

申请人： Ronald Kakoschke ,  Thomas Nirschl ,  Danny Shum ,  Klaus Schrüfer

发明人： Ronald Kakoschke ,  Thomas Nirschl ,  Danny Shum ,  Klaus Schrüfer

IPC分类号： H01L29/788

CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L29/8616

摘要： A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions.

摘要翻译： 提出了使用隧道场效应晶体管（TFET）和掩埋位线的存储器件。 存储器件包括包含存储单元的行和列的矩阵。 每个存储单元包含至少一个单元晶体管，其又包含第一掺杂区域和第二掺杂区域，其中一个是源极，另一个是漏极区域。 存储器件包括字线，每条字线连接到一行的存储单元和位线，每一行连接到一列的存储单元。 第一掺杂区域具有与第二掺杂区域不同的掺杂类型。

公开(公告)号：US20110171803A1

公开(公告)日：2011-07-14

申请号：US13052728

申请日：2011-03-21

申请人： Ronald Kakoschke ,  Thomas Nirschl ,  Danny Shum ,  Klaus Schrüfer

发明人： Ronald Kakoschke ,  Thomas Nirschl ,  Danny Shum ,  Klaus Schrüfer

IPC分类号： H01L21/336

CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L29/8616

摘要： A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions.

摘要翻译： 提出了使用隧道场效应晶体管（TFET）和掩埋位线的存储器件。 存储器件包括包含存储单元的行和列的矩阵。 每个存储单元包含至少一个单元晶体管，其又包含第一掺杂区域和第二掺杂区域，其中一个是源极，另一个是漏极区域。 存储器件包括字线，每条字线连接到一行的存储单元和位线，每一行连接到一列的存储单元。 第一掺杂区域具有与第二掺杂区域不同的掺杂类型。