公开(公告)号：US5508534A

公开(公告)日：1996-04-16

申请号：US384734

申请日：1995-02-07

申请人： Katsumi Nakamura ,  Tadaharu Minato ,  Shuuichi Tominga ,  Katsuomi Shiozawa

发明人： Katsumi Nakamura ,  Tadaharu Minato ,  Shuuichi Tominga ,  Katsuomi Shiozawa

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/417 ,  H01L29/739 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L29/7813 ,  H01L29/41716 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7455 ,  H01L29/749 ,  Y10S148/011 ,  Y10S148/05 ,  Y10S148/133 ,  Y10S438/978

摘要： A semiconductor device including a layer formed without being affected by a stepped ground pattern and a method of fabricating the semiconductor device are disclosed. Cap portions (30) (insulating layers) formed over trenches (13) and covering doped polysilicon (5) have an inclined surface (26) which satisfies Y/X .ltoreq.5 where X is the length of the inclined surface (26) in a direction of the surface of a body (50) and Y is the height of the inclined surface (26) from the surface of the body (50). Formation of the insulating layers having the smooth inclined surface satisfying Y/X.ltoreq.5 permits a first main electrode to be formed non-defectively without being affected by the ground pattern including the insulating layers.

摘要翻译： 公开了一种半导体器件，其包括不受阶梯状接地图案形成的层，以及制造该半导体器件的方法。 形成在沟槽（13）上并覆盖掺杂多晶硅（5）的盖部分（30）（绝缘层）具有满足Y /X≤5的倾斜表面（26），其中X是倾斜表面（26）的长度， 在主体（50）的表面的方向上，Y是从主体（50）的表面的倾斜表面（26）的高度。 具有满足Y /X≤5的平滑倾斜面的绝缘层的形成允许第一主电极无缺陷地形成，而不受包括绝缘层的接地图案的影响。

公开(公告)号：US5414301A

公开(公告)日：1995-05-09

申请号：US197359

申请日：1994-02-16

申请人： Michael E. Thomas

发明人： Michael E. Thomas

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48 ,  H01L29/40 ,  H01L29/96 ,  H01L29/62

CPC分类号： H01L21/76885 ,  H01L21/76819 ,  H01L21/76877 ,  H01L23/53257 ,  H01L2924/0002 ,  Y10S148/133

摘要： A semiconductor integrated circuit device is provided with an electrical interconnect system which is stable at high temperatures. The interconnect system employs refractory metal compounds which are electrically conductive, which form stable couples with silicon and compounds thereof, and which remain stable at temperatures exceeding approximately 500.degree. C.

公开(公告)号：US5054683A

公开(公告)日：1991-10-08

申请号：US576328

申请日：1990-08-29

申请人： Jan Haisma ,  Gijsbertus Spierings ,  Joseph G. Van Lierop ,  Hendrik F. Van Den Berg

发明人： Jan Haisma ,  Gijsbertus Spierings ,  Joseph G. Van Lierop ,  Hendrik F. Van Den Berg

IPC分类号： C04B37/00 ,  C04B37/04 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/2007 ,  Y10S148/133 ,  Y10S228/903

摘要： A method is set forth of bonding together two bodies (1, 2), according to which a first body (1) is provided with a flat surface (5) and the second body (2) is provided with a silicon oxide layer (4) with a flat surface (6), after which a connecting layer (7) containing boron is provided on at least one of the two flat surfaces. Subsequently, the two bodies (1, 2) are pressed together at elevated temperature, so that a borosilicate glass layer is formed. According to the invention, a layer of practically pure boron is used by way of connecting layer (7). Among the advantages of this is that the composition of the borosilicate glass layer is exclusively determined by the previously chosen layer thicknesses.

摘要翻译： 提出了一种将两个主体（1,2）接合在一起的方法，根据该主体，第一主体（1）设置有平坦表面（5），并且第二主体（2）设置有氧化硅层（4） ），之后在两个平坦表面中的至少一个上提供含有硼的连接层（7）。 随后，将两个体（1,2）在升高的温度下压在一起，从而形成硼硅酸盐玻璃层。 根据本发明，通过连接层（7）使用实际上纯硼的层。 其优点之一是硼硅酸盐玻璃层的组成仅由先前选择的层厚决定。

公开(公告)号：US5047369A

公开(公告)日：1991-09-10

申请号：US345924

申请日：1989-05-01

申请人： Debra A. Fleming ,  David W. Johnson, Jr. ,  Shobha Singh ,  LeGrand G. VanUitert ,  George J. Zydzik

发明人： Debra A. Fleming ,  David W. Johnson, Jr. ,  Shobha Singh ,  LeGrand G. VanUitert ,  George J. Zydzik

IPC分类号： C03C3/062 ,  C03C3/097 ,  H01L21/314 ,  H01L21/316

CPC分类号： H01L21/02129 ,  H01L21/02266 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/31625 ,  Y10S148/133 ,  Y10S438/902

摘要： This invention is directed to a process of producing semiconductor devices which involves deposition of protective glass layers by a particle beam technique from targets of phosphosilicate glass, as well as a process for production of such targets. The phosphosilicate glass containing 1-15 mole percent P.sub.2 O.sub.5 is produced by a sol/gel technique which involves mixing of a fumed silica, with a surface area of 50-400 m.sup.2 /g, preferably about 200 m.sup.2 /g, with phosphoric acid and water to form a sol with 20-55 wt. % silica, allowing it to gel, drying at ambient conditions, dehydrating at about 650.degree. C. in an atmosphere of an inert gas and chlorine and fluorine containing gases, heating up at a certain rate of from 100.degree. to 180.degree. C. per hour to a peak sintering temperature below 1200.degree. C. and cooling so as to produce amorphous and transparent glass suitable for use as a target. The glass layers are highly advantageous as encapsulating layers, diffusion barrier layers, etc., especially for optical type and semiconductor devices. Production of the phosphosilicate glass by the sol/gel technique is highly advantageous over the conventional melting technique, being faster and much less expensive than the latter.

公开(公告)号：US5006484A

公开(公告)日：1991-04-09

申请号：US472765

申请日：1990-01-31

申请人： Yusuke Harada

发明人： Yusuke Harada

IPC分类号： H01L21/768

CPC分类号： H01L21/76802 ,  Y10S148/133 ,  Y10S438/97

摘要： In a process of fabrication of a semiconductor device having a relatively deep contact hole and a relatively shallow contact hole; a lower interlayer insulating layer is formed on a semiconductor substrate, and then subjected to heat treatment to flow; an upper interlayer insulating film is then formed on the lower interlayer insulating film, and is then subjected to heat treatment to flow; a non-flowing film which does not flow is then formed in the area where the shallow contact hole will be formed; and the deep and the shallow holes are then formed through the upper interlayer insulating film and the non-flowing film and heat treatment is conducted to cause flow of the upper interlayer insulating film whereby the flow of the upper interlayer insulating layer occurs except at the area covered by the non-flowing film. The deep and the shallow contact holes are then filled with metal by selective CVD; and an interconnection is then formed to have contact with the metal filling the contact holes.

摘要翻译： 在制造具有相对较深的接触孔和较浅接触孔的半导体器件的过程中; 在半导体基板上形成下层间绝缘层，然后进行热处理流动; 然后在下层间绝缘膜上形成上层间绝缘膜，然后进行热处理流动; 然后在将形成浅接触孔的区域中形成不流动的不流动膜; 然后通过上层间绝缘膜和非流动膜形成深孔和浅孔，并进行热处理以引起上层间绝缘膜的流动，由此上层间绝缘层的流动发生在区域外 被不流动的电影覆盖。 深孔和浅接触孔然后通过选择性CVD填充金属; 然后形成与填充接触孔的金属接触的互连。

公开(公告)号：US5004704A

公开(公告)日：1991-04-02

申请号：US428903

申请日：1989-10-30

申请人： Satoshi Maeda ,  Shizuo Sawada

发明人： Satoshi Maeda ,  Shizuo Sawada

IPC分类号： H01L21/3205 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/52

CPC分类号： H01L21/76837 ,  H01L21/31051 ,  H01L21/76834 ,  Y10S148/133

摘要： A Phospho Silicate Glass layer is used for an insulation layer between a lower wiring layer including a refractory metal silicide and an upper wiring layer in a semiconductor device of a multilevel interconnection structure. A reflow treatment is performed on the Phospho Silicate Glass layer using steam. A part of the lower wiring layer is oxidized during the reflow treatment, and the resistivity of the lower wiring layer is simultaneously lowered during the reflow treatment.

公开(公告)号：US4948743A

公开(公告)日：1990-08-14

申请号：US373102

申请日：1989-06-29

申请人： Hideto Ozaki

发明人： Hideto Ozaki

IPC分类号： H01L21/768

CPC分类号： H01L21/76804 ,  Y10S148/133

摘要： A method of manufacturing a semiconductor device, includes the following steps: part of an insulation film is left on the bottom of a contact hole of the insulation film formed on a semiconductor substrate or a separate insulation film is otherwise formed, under which condition a satisfactory slope is formed on the peripheral edge and the side wall of the contact hold by providing the semiconductor substrate with a heat treatment. According to the present invention, it is possible thereafter to improve the step coverage of a metal interconnection to be formed on the surface of the insulation film and to prevent breakage of the metal interconnection, thereby substantially improving the reliability of the resulting semiconductor device.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：绝缘膜的一部分留在半导体衬底上形成的绝缘膜的接触孔的底部，否则形成单独的绝缘膜，在该条件下，令人满意的 通过对半导体衬底进行热处理，在接触保持的周缘和侧壁上形成斜面。 根据本发明，可以改善在绝缘膜的表面上形成的金属互连的阶梯覆盖，并且防止金属互连的断裂，从而显着提高所得到的半导体器件的可靠性。

公开(公告)号：US4920071A

公开(公告)日：1990-04-24

申请号：US86200

申请日：1987-08-18

申请人： Michael E. Thomas

发明人： Michael E. Thomas

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76885 ,  H01L21/76819 ,  H01L21/76877 ,  H01L23/53257 ,  H01L2924/0002 ,  Y10S148/133

摘要： A semiconductor integrated circuit device is provided with an electrical interconnect system which is stable at high temperatures. The interconnect system employs refractory metal compounds which are electrically conductive, which form stable couples with silicon and compounds thereof, and which remain stable at temperatures exceeding approximately 500.degree. C.

摘要翻译： 半导体集成电路器件具有在高温下稳定的电互连系统。 互连系统采用导电的难熔金属化合物，其与硅和其化合物形成稳定的配对，并且在超过约500℃的温度下保持稳定。

公开(公告)号：US4892845A

公开(公告)日：1990-01-09

申请号：US646559

申请日：1984-08-31

申请人： Jeffrey M. Bridges

发明人： Jeffrey M. Bridges

IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L23/485

CPC分类号： H01L21/31116 ,  H01L21/76885 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/133

摘要： A method for fabricating contacts in a semiconductor substrate includes forming a thin buffer oxide layer (26) over a substrate (10) with active devices defined therein. Access openings (28), (30) and (32) are then formed in the thin oxide layer (26) and then aluminum columnar contacts (38), (40) and (42) formed therein with a predetermined height. A thick oxide layer of phosphorous silicate glass (50) is then formed over the built-up structure. A planarizing resist layer (52) is formed over top of the structure with a substantially thinner area defined proximate the upper surfaces of the columnar contacts (38, 40, 42). The thin areas (54, 56, 58) are removed by selectively etching away the upper surface of the resist layer (52) by an excited plasma process. The structure is then subjected to a phosphorous selective etch to remove only those portions of the thick oxide layer (52') proximate the upper surfaces of the columnar contacts (38, 40, 42). Interconnects are then formed on the surface for connection with the exposed surface of the columnar contacts.

摘要翻译： 一种用于在半导体衬底中制造接触的方法包括在其上限定有活性器件的基底（10）上形成薄的缓冲氧化物层（26）。 然后在薄氧化物层（26）中形成入口（28），（30）和（32），然后在其中形成预定高度的铝柱状接触件（38），（40）和（42）。 然后在积层结构上形成磷酸硅酸盐玻璃（50）的厚氧化物层。 平面化抗蚀剂层（52）形成在结构的顶部上，具有在柱形触点（38,40,42）的上表面附近限定的基本更薄的区域。 通过用激发的等离子体工艺选择性蚀刻掉抗蚀剂层（52）的上表面，去除薄区域（54,56,58）。 然后对该结构进行磷选择性蚀刻以仅去除靠近柱状触点（38,40,42）的上表面的厚氧化物层（52'）的那些部分。 然后在表面上形成互连件以与柱状触点的暴露表面连接。

公开(公告)号：US4795722A

公开(公告)日：1989-01-03

申请号：US10937

申请日：1987-02-05

申请人： Michael T. Welch ,  Ronald E. McMann ,  Manuel L. Torreno, Jr. ,  Evaristo Garcia, Jr. ,  Jeffrey E. Brighton

发明人： Michael T. Welch ,  Ronald E. McMann ,  Manuel L. Torreno, Jr. ,  Evaristo Garcia, Jr. ,  Jeffrey E. Brighton

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/90 ,  H01L23/48 ,  H01L29/46

CPC分类号： H01L21/76877 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76819 ,  Y10S148/011 ,  Y10S148/043 ,  Y10S148/133 ,  Y10S148/147

摘要： A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of the platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar. Contact vias are etched through the undoped and doped oxides; the silicide film acts as an etch stop, allowing contacts of differing depths to be etched from the planar top surface of the undoped oxide without etching through any of the polysilicon layers to which contact is to be made. A metal such as tungsten is deposited onto the slice to fill the contact vias, and is planarized in the same fashion as was the undoped oxide. The metallization is then sputtered onto the planar surface presented by the planarized undoped oxide and the planarized tungsten, and is patterned and etched to form the desired interconnection pattern.

摘要翻译： 公开了一种在其金属化之前对半导体薄片进行平坦化的方法。 处理半导体片以便使用公知的技术形成扩散和下面的互连层。 在金属化之前沉积和图案化最后的互连层之后，将铂或另一种金属层沉积在切片上。 将切片烧结以在直接暴露于溅射铂的互连层和扩散部分上形成硅化物膜。 然后沉积一层磷掺杂电介质，随后是一层未掺杂的氧化物。 将光致抗蚀剂或其他保形材料旋转到切片上，得到平坦的顶表面。 将切片暴露于等离子体蚀刻，其蚀刻光致抗蚀剂和未掺杂的氧化物，导致基本上为平面的未掺杂氧化物的顶表面。 接触孔通过未掺杂和掺杂的氧化物蚀刻; 硅化物膜用作蚀刻停止件，允许从未掺杂的氧化物的平坦顶表面蚀刻不同深度的接触，而不蚀刻通过要进行接触的任何多晶硅层。 将诸如钨的金属沉积在切片上以填充接触孔，并且以与未掺杂的氧化物相同的方式被平坦化。 然后将金属化溅射到由平坦化未掺杂的氧化物和平坦化钨呈现的平坦表面上，并被图案化和蚀刻以形成所需的互连图案。