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公开(公告)号：US06781436B2
公开(公告)日：2004-08-24
申请号：US10202943
申请日：2002-07-25
IPC分类号： H01H3776
摘要： A transistor (such as a MOSFET) is operated in its breakdown region, as opposed to its saturation region, to program an electric fuse. With the programming transistor operated in the breakdown region, a much higher current is enabled than the associated saturation current for the same size transistor. Thus, a smaller transistor can be used for programming the fuse. Cooperative with transistor operation in the breakdown region, a dynamic current compliance device is used to limit the peak current to prevent damage than can result from excessive current flowing through the transistor. The current compliance device can be external to the integrated fuse and programming transistor circuit.
摘要翻译： 晶体管（例如MOSFET）在其击穿区域中操作，与其饱和区域相反，以对电熔丝进行编程。 在编程晶体管工作在击穿区域的情况下，相同尺寸晶体管的相关饱和电流能够实现更高的电流。 因此，可以使用较小的晶体管来编程保险丝。 与击穿区域中的晶体管工作合作，使用动态电流一致性装置来限制峰值电流，以防止由过大的电流流过晶体管而导致的损坏。 电流兼容装置可以在集成保险丝和编程晶体管电路外部。
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公开(公告)号：US06710640B1
公开(公告)日：2004-03-23
申请号：US10247154
申请日：2002-09-19
IPC分类号： H01H3776
CPC分类号： G11C17/18
摘要： A transistor (such as a MOSFET) is operated with the well biased, as opposed to being grounded, to program an electric fuse. With the programming transistor operated with an active well bias, more energy is enabled for programming the fuse than is available with a grounded well for the same size transistor. Thus, a smaller transistor can be used of programming the fuse. In a multiple fuse embodiment, the programming transistors can be arranged in the same “well” with a common independent Vbias applied, via a body control circuit, to the entire well during programming of a select fuse.
摘要翻译： 晶体管（例如MOSFET）与阱极化相反，而不是接地，以对电熔丝进行编程。 由于编程晶体管采用有源阱偏置电压工作，因此对于相同尺寸的晶体管，能够为熔丝编程提供更多的能量，而不需要接地的阱。 因此，可以使用较小的晶体管来编程保险丝。 在多熔丝实施例中，编程晶体管可以被布置在相同的“阱”中，在选择熔丝的编程期间，经由主体控制电路将普通的独立Vbias布置到整个阱。
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3.发明授权System for programming fuse structure by electromigration of silicide enhanced by creating temperature gradient 有权通过产生温度梯度增强硅化物电迁移来编程熔丝结构的系统公开(公告)号：US06624499B2
公开(公告)日：2003-09-23
申请号：US10247415
申请日：2002-09-19
申请人： Chandrasekharan Kothandaraman , S. Sundar Kumar Iyer , Subramanian Iyer , Chandrasekhar Narayan
发明人： Chandrasekharan Kothandaraman , S. Sundar Kumar Iyer , Subramanian Iyer , Chandrasekhar Narayan
IPC分类号： H01L2900
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode coupled by a fuse link having an electrically conductive component, such as silicide, is coupled to a power supply. A potential is applied across the conductive fuse link via the cathode and anode in which the potential is of a magnitude to initiate electromigration of silicide from a region of the semiconductor fuse reducing the conductivity of the fuse link. The electromigration is enhanced by effectuating a temperature gradient between the fuse link and one of the cathode and anode responsive to the applied potential. Portions of the semiconductor fuse are selectively cooled in a heat transfer relationship to increase the temperature gradient. In one embodiment, a heat sink is applied to the cathode. The heat sink can be a layer of metal coupled in close proximity to the cathode while insulated from the fuse link. In another embodiment, the temperature gradient is increased by selectively varying the thickness of the underlying oxide layer such that the cathode is disposed on a thinner layer of oxide than the fuse link.
摘要翻译： 本发明提供一种通过电迁移编程的系统，装置和方法。 包括阴极和由具有诸如硅化物之类的导电部件的熔丝连接的阳极的半导体熔丝被耦合到电源。 电势通过阴极和阳极施加在导电熔丝连接上，其中电位为大小以引发硅化物从半导体熔丝的区域的电迁移，从而降低熔丝链的导电性。 响应于所施加的电位，通过实现熔丝链和阴极和阳极中的一个之间的温度梯度来增强电迁移。 半导体保险丝的一部分以热传递关系被选择性地冷却以增加温度梯度。 在一个实施例中，将散热器施加到阴极。 散热器可以是在与熔丝连接绝缘的情况下紧邻阴极耦合的金属层。 在另一个实施方案中，通过选择性地改变下面的氧化物层的厚度使得阴极设置在比熔丝链更薄的氧化物层上来增加温度梯度。
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公开(公告)号：US06998865B2
公开(公告)日：2006-02-14
申请号：US10013789
申请日：2001-12-10
CPC分类号： G01R31/2884
摘要： A test arrangement includes a semiconductor device, a first conductive pad electrically connected to the semiconductor device, a second conductive pad, and a programmable fuse. The second conductive pad is electrically connected to the semiconductor device through the programmable fuse.
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公开(公告)号：US6096580A
公开(公告)日：2000-08-01
申请号：US405331
申请日：1999-09-24
IPC分类号： H01L23/525 , H01L21/82
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： A low programming voltage anti-fuse formed by a MOSFET (or MOS) or by a deep trench (DT) capacitor structure is described. Lowering the programming voltage is achieved by implanting a dose of heavy ions, such as indium, into the dielectric directly on the substrate or indirectly through a layer of polysilicon. The programming voltage can also be lowered on the MOSFET/MOS capacitor anti-fuse by accentuating the corners of active areas and gate areas of the device with suitable layout masks during processing. Silicon active area corner rounding steps should also be avoided in the fabrication of the anti-fuse to reduce the programming voltage. In the DT capacitor, lowering the programming voltage may be achieved by implanting the node dielectric of the DT anti-fuse with heavy ions either directly or through a conformal layer of polysilicon deposited on it or after the first amorphous silicon recess step during the fabrication of the DT capacitor.
摘要翻译： 描述了由MOSFET（或MOS）或深沟槽（DT）电容器结构形成的低编程电压反熔丝。 降低编程电压可以通过将一定剂量的重离子（如铟）直接注入到基底上的电介质或间接通过多晶硅层来实现。 通过在处理期间通过适当的布局掩模强调器件的有源区域和栅极区域的角，也可以在MOSFET / MOS电容器反熔丝上降低编程电压。 在制造抗熔丝的同时，也应避免硅有源区四舍五入步骤，以减少编程电压。 在DT电容器中，降低编程电压可以通过直接或通过沉积在其上的多晶硅的保形层或在第一非晶硅凹槽步骤之后的重离子注入DT反熔丝的节点电介质来实现， DT电容器。
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6.发明授权公开(公告)号：US06486043B1
公开(公告)日：2002-11-26
申请号：US09652711
申请日：2000-08-31
IPC分类号： H01L2120
CPC分类号： H01L21/76264 , H01L21/76267 , H01L21/76283
摘要： A method for forming a semiconductor devices structure includes providing a semiconductor substrate, forming a deep trench continuously in the substrate to separate a first region from a second region, and then forming a silicon-on-insulator region in the first region while maintaining a non-silicon-on-insulator region in the second region. The deep trench has a depth which is at least as deep as the depth of the buried oxide in the substrate. The invention also includes a device structure resulting from the method.
摘要翻译： 一种用于形成半导体器件结构的方法包括提供半导体衬底，在衬底中连续形成深沟槽以将第一区域与第二区域分离，然后在第一区域中形成绝缘体上硅区域，同时保持非 - - 第二区域中的绝缘体上硅区域。 深沟槽的深度至少与衬底中的掩埋氧化物的深度一样深。 本发明还包括由该方法得到的装置结构。
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