公开(公告)号：US6096580A

公开(公告)日：2000-08-01

申请号：US405331

申请日：1999-09-24

申请人： S. Sundar Kumar Iyer ,  Liang-Kai Han ,  Robert Hannon ,  Subramanian S. Iyer ,  Mukesh V. Khare

发明人： S. Sundar Kumar Iyer ,  Liang-Kai Han ,  Robert Hannon ,  Subramanian S. Iyer ,  Mukesh V. Khare

IPC分类号： H01L23/525 ,  H01L21/82

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： A low programming voltage anti-fuse formed by a MOSFET (or MOS) or by a deep trench (DT) capacitor structure is described. Lowering the programming voltage is achieved by implanting a dose of heavy ions, such as indium, into the dielectric directly on the substrate or indirectly through a layer of polysilicon. The programming voltage can also be lowered on the MOSFET/MOS capacitor anti-fuse by accentuating the corners of active areas and gate areas of the device with suitable layout masks during processing. Silicon active area corner rounding steps should also be avoided in the fabrication of the anti-fuse to reduce the programming voltage. In the DT capacitor, lowering the programming voltage may be achieved by implanting the node dielectric of the DT anti-fuse with heavy ions either directly or through a conformal layer of polysilicon deposited on it or after the first amorphous silicon recess step during the fabrication of the DT capacitor.

摘要翻译： 描述了由MOSFET（或MOS）或深沟槽（DT）电容器结构形成的低编程电压反熔丝。 降低编程电压可以通过将一定剂量的重离子（如铟）直接注入到基底上的电介质或间接通过多晶硅层来实现。 通过在处理期间通过适当的布局掩模强调器件的有源区域和栅极区域的角，也可以在MOSFET / MOS电容器反熔丝上降低编程电压。 在制造抗熔丝的同时，也应避免硅有源区四舍五入步骤，以减少编程电压。 在DT电容器中，降低编程电压可以通过直接或通过沉积在其上的多晶硅的保形层或在第一非晶硅凹槽步骤之后的重离子注入DT反熔丝的节点电介质来实现， DT电容器。

公开(公告)号：US06297127B1

公开(公告)日：2001-10-02

申请号：US09599699

申请日：2000-06-22

申请人： Bomy A. Chen ,  Liang-Kai Han ,  Robert Hannon ,  Jay G. Harrington ,  Herbert L. Ho ,  Hsing-Jen Wann

发明人： Bomy A. Chen ,  Liang-Kai Han ,  Robert Hannon ,  Jay G. Harrington ,  Herbert L. Ho ,  Hsing-Jen Wann

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： Shallow trench isolation is combined with optional deep trenches that are self-aligned with the shallow trenches, at the corners of the shallow trenches, and have a deep trench width that is controlled by the thickness of a temporary sidewall deposited in the interior of the shallow trench and is limited by the sidewall deposition thickness of the deep trench fill.

摘要翻译： 浅沟槽隔离与在浅沟槽的角部处与浅沟槽自对准的可选深沟槽组合，并且具有深沟槽宽度，其由沉积在浅层的内部中的临时侧壁的厚度控制 并且受到深沟槽填充物的侧壁沉积厚度的限制。

公开(公告)号：US08633086B2

公开(公告)日：2014-01-21

申请号：US12651322

申请日：2009-12-31

申请人： Alex Kalnitsky ,  Hsiao-Chin Tuan ,  Liang-Kai Han ,  Uway Tseng ,  Yuan-Chih Hsieh ,  Hung-Hua Lin

发明人： Alex Kalnitsky ,  Hsiao-Chin Tuan ,  Liang-Kai Han ,  Uway Tseng ,  Yuan-Chih Hsieh ,  Hung-Hua Lin

IPC分类号： H01L21/30

CPC分类号： H01L29/66712 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a support structure for supporting and handling a semiconductor wafer containing vertical FETs formed at the front surface thereof is provided. In one embodiment, a semiconductor wafer is provided having a front surface and a rear surface, wherein the front surface comprises one or more dies separated by dicing lines. The wafer is thinned to a predetermined thickness. A plurality of patterned metal features are formed on a thinned rear surface to provide support for the wafer, wherein each of the plurality of patterned metal features covers substantially one die, leaving the dicing lines substantially uncovered. The wafer is thereafter diced along the dicing lines to separate the one or more dies for later chip packaging.

摘要翻译： 提供一种形成用于支撑和处理包含形成在其前表面上的垂直FET的半导体晶片的支撑结构的方法。 在一个实施例中，提供具有前表面和后表面的半导体晶片，其中前表面包括由切割线分开的一个或多个裸片。 将晶片减薄至预定厚度。 多个图案化的金属特征形成在薄的后表面上以提供对晶片的支撑，其中多个图案化的金属特征中的每一个基本上覆盖一个管芯，使切割线基本上不被覆盖。 然后，晶片沿着切割线切割，以分离一个或多个模具用于稍后的芯片封装。

公开(公告)号：US07534671B2

公开(公告)日：2009-05-19

申请号：US12058664

申请日：2008-03-29

申请人： Chiang-Ming Chuang ,  Liang-Kai Han

发明人： Chiang-Ming Chuang ,  Liang-Kai Han

IPC分类号： H01L21/338 ,  H01L21/336

CPC分类号： H01L27/0629 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. A dielectric layer is deposited over the isolation structure and the semiconductor substrate. A metal layer is deposited on the dielectric layer. A polysilicon layer is deposited on the metal layer. The dielectric layer, the metal layer and the polysilicon layer are patterned into a first stack of the dielectric layer, the metal layer and the polysilicon layer on the isolation structure for functioning as the electrical fuse device, and a second stack of the dielectric layer, the metal layer and the polysilicon layer on the semiconductor substrate for functioning as a gate of the MOS device.

摘要翻译： 在半导体衬底上整体形成金属氧化物半导体（MOS）器件和电熔丝器件的方法包括以下步骤。 在半导体衬底上形成隔离结构。 绝缘层沉积在隔离结构和半导体衬底上。 金属层沉积在电介质层上。 多晶硅层沉积在金属层上。 电介质层，金属层和多晶硅层被图案化为隔离结构上的电介质层，金属层和多晶硅层的第一堆叠，用作电熔丝器件，以及介电层的第二堆叠， 半导体衬底上的金属层和多晶硅层，用作MOS器件的栅极。

公开(公告)号：US07183596B2

公开(公告)日：2007-02-27

申请号：US11158764

申请日：2005-06-22

申请人： I-Lu Wu ,  Kuang-Hsin Chen ,  Liang-Kai Han

发明人： I-Lu Wu ,  Kuang-Hsin Chen ,  Liang-Kai Han

IPC分类号： H01L29/76

CPC分类号： H01L21/823842 ,  H01L21/823857 ,  H01L29/785

摘要： An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.

摘要翻译： 提供一种具有复合栅结构的集成电路及其形成方法。 集成电路包括第一MOS器件，第二MOS器件和第三MOS器件。 第一MOS器件的栅极堆叠包括高k栅极电介质和高k栅极电介质上的第一金属栅极。 第二MOS器件的栅极堆叠包括在高k栅极电介质上的第二金属栅极。 第一金属门和第二金属门具有不同的功能。 第三MOS器件的栅极堆叠包括栅极电介质上的硅栅极。 硅栅极优选形成在第一MOS器件和第二MOS器件的栅极堆叠之上。

公开(公告)号：US06885080B2

公开(公告)日：2005-04-26

申请号：US10082648

申请日：2002-02-22

申请人： Tze-Chiang Chen ,  Liang-Kai Han

发明人： Tze-Chiang Chen ,  Liang-Kai Han

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/092 ,  H01L27/108 ,  H01L29/00

CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/76232 ,  H01L27/10829 ,  H01L27/10897

摘要： A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.

摘要翻译： 公开了一种用于阻止在半导体器件中产生的缺陷传播的保护结构。 在示例性实施例中，该结构包括在半导体器件的存储器存储区域和半导体器件的逻辑电路区域之间形成的深沟槽隔离，深沟槽隔离件填充有绝缘材料。 深沟槽隔离从而防止在逻辑电路区域中产生的晶体缺陷的传播不会传播到存储器存储区域中。

公开(公告)号：US20120181612A1

公开(公告)日：2012-07-19

申请号：US13005681

申请日：2011-01-13

申请人： Jing-Hwang Yang ,  Chun-Heng Liao ,  Hsin-Li Cheng ,  Liang-Kai Han

发明人： Jing-Hwang Yang ,  Chun-Heng Liao ,  Hsin-Li Cheng ,  Liang-Kai Han

IPC分类号： H01L29/40 ,  H01L21/3205

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0802

摘要： The present disclosure involves a method. The method includes providing a substrate including a top surface. The method also includes forming a gate over the top surface of the substrate. The formed gate has a first height measured from the top surface of the substrate. The method also includes etching the gate to reduce the gate to a second height. This second height is substantially less than the first height. The present disclosure also involves a semiconductor device. The semiconductor device includes a substrate. The substrate includes a top surface. The semiconductor device also includes a first gate formed over the top surface of the substrate. The first gate has a first height. The semiconductor device also includes a second gate formed over the top surface of the substrate. The second gate has a second height. The first height is substantially less than the second height.

摘要翻译： 本公开涉及一种方法。 该方法包括提供包括顶表面的基底。 该方法还包括在衬底的顶表面上形成栅极。 形成的栅极具有从基板的顶表面测量的第一高度。 该方法还包括蚀刻栅极以将栅极减小到第二高度。 该第二高度明显小于第一高度。 本公开还涉及半导体器件。 半导体器件包括衬底。 衬底包括顶表面。 半导体器件还包括形成在衬底顶表面上的第一栅极。 第一个门有一个第一高度。 半导体器件还包括形成在衬底顶表面上的第二栅极。 第二个门有第二个高度。 第一高度大致小于第二高度。

公开(公告)号：US20110156217A1

公开(公告)日：2011-06-30

申请号：US12651322

申请日：2009-12-31

申请人： Alex Kalnitsky ,  Hsiao-Chin Tuan ,  Liang-Kai Han ,  Uway Tseng ,  Yuan-Chih Hsieh ,  Hung-Hua Lin

发明人： Alex Kalnitsky ,  Hsiao-Chin Tuan ,  Liang-Kai Han ,  Uway Tseng ,  Yuan-Chih Hsieh ,  Hung-Hua Lin

IPC分类号： H01L23/58 ,  H01L21/78

CPC分类号： H01L29/66712 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a support structure for supporting and handling a semiconductor wafer containing vertical FETs formed at the front surface thereof is provided. In one embodiment, a semiconductor wafer is provided having a front surface and a rear surface, wherein the front surface comprises one or more dies separated by dicing lines. The wafer is thinned to a predetermined thickness. A plurality of patterned metal features are formed on a thinned rear surface to provide support for the wafer, wherein each of the plurality of patterned metal features covers substantially one die, leaving the dicing lines substantially uncovered. The wafer is thereafter diced along the dicing lines to separate the one or more dies for later chip packaging.

摘要翻译： 提供一种形成用于支撑和处理包含形成在其前表面上的垂直FET的半导体晶片的支撑结构的方法。 在一个实施例中，提供具有前表面和后表面的半导体晶片，其中前表面包括由切割线分开的一个或多个裸片。 将晶片减薄至预定厚度。 多个图案化的金属特征形成在薄的后表面上以提供对晶片的支撑，其中多个图案化的金属特征中的每一个基本上覆盖一个管芯，使切割线基本上不被覆盖。 然后，晶片沿着切割线切割，以分离一个或多个模具用于稍后的芯片封装。

公开(公告)号：US20080182373A1

公开(公告)日：2008-07-31

申请号：US12058664

申请日：2008-03-29

申请人： Chiang-Ming Chuang ,  Liang-Kai Han

发明人： Chiang-Ming Chuang ,  Liang-Kai Han

IPC分类号： H01L21/8234

CPC分类号： H01L27/0629 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. A dielectric layer is deposited over the isolation structure and the semiconductor substrate. A metal layer is deposited on the dielectric layer. A polysilicon layer is deposited on the metal layer. The dielectric layer, the metal layer and the polysilicon layer are patterned into a first stack of the dielectric layer, the metal layer and the polysilicon layer on the isolation structure for functioning as the electrical fuse device, and a second stack of the dielectric layer, the metal layer and the polysilicon layer on the semiconductor substrate for functioning as a gate of the MOS device.

摘要翻译： 在半导体衬底上整体形成金属氧化物半导体（MOS）器件和电熔丝器件的方法包括以下步骤。 在半导体衬底上形成隔离结构。 绝缘层沉积在隔离结构和半导体衬底上。 金属层沉积在电介质层上。 多晶硅层沉积在金属层上。 电介质层，金属层和多晶硅层被图案化为隔离结构上的电介质层，金属层和多晶硅层的第一堆叠，用作电熔丝器件，以及介电层的第二堆叠， 半导体衬底上的金属层和多晶硅层，用作MOS器件的栅极。

公开(公告)号：US20070114604A1

公开(公告)日：2007-05-24

申请号：US11286003

申请日：2005-11-22

申请人： Huan-Tsung Huang ,  Liang-Kai Han

发明人： Huan-Tsung Huang ,  Liang-Kai Han

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A MOS transistor structure is disclosed. A gate electrode is disposed on a semiconductor substrate. A first extension of a predetermined impurity type is substantially aligned with the gate electrode in the substrate. A second extension of the predetermined impurity type overlaps with the first extension in the substrate. The first extension has at least one lateral boundary line closer to the gate electrode than that of the second extension. Source and drain regions of the predetermined polarity type overlaps with the first and second extensions in the substrate. The second extension has at least one lateral boundary line closer to the gate electrode than that of the source and drain regions. The source and drain regions are deeper than the second extension, which is deeper than the first extension, so that they collectively reduce lateral abruptness of the source and drain, while maintaining a reduced extension resistance.

摘要翻译： 公开了一种MOS晶体管结构。 栅电极设置在半导体衬底上。 预定杂质类型的第一延伸部基本上与衬底中的栅电极对准。 预定杂质类型的第二延伸部与衬底中的第一延伸部重叠。 第一延伸部具有比第二延伸部更靠近栅电极的至少一个横向边界线。 预定极性类型的源区和漏区与衬底中的第一和第二延伸部重叠。 第二延伸部具有比源极和漏极区域更靠近栅电极的至少一个横向边界线。 源极和漏极区域比第二延伸部更深，其比第一延伸部更深，使得它们共同地减小源极和漏极的横向突然，同时保持降低的延伸电阻。