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    Semiconductor memory devices having conductive line in twisted areas of twisted bit line pairs
    2.
    发明授权
    Semiconductor memory devices having conductive line in twisted areas of twisted bit line pairs 失效
    半导体存储器件在绞合位线对的扭转区域具有导线

    公开(公告)号：US07242602B2

    公开(公告)日：2007-07-10

    申请号：US11002034

    申请日：2004-12-02

    申请人： Chang-Ho Lee ,  Jong-Hyun Choi

    发明人： Chang-Ho Lee ,  Jong-Hyun Choi

    IPC分类号： G11C5/08 ,  G11C5/06 ,  G11C11/12

    CPC分类号： G11C11/4097 ,  G11C5/14 ,  G11C7/02 ,  Y10S257/907

    摘要： A semiconductor memory device includes spaced apart twisted bit line pairs, a respective one of which includes a spaced apart twisted area. A conductive line overlaps the respective twisted areas of the spaced apart twisted line pairs. The conductive line can extend parallel to the memory device word lines, and can provide a power supply ground and/or signal line.

    摘要翻译： 半导体存储器件包括间隔开的扭曲位线对，其相应的一个包括间隔开的扭曲区域。 导线与间隔开的扭绞线对的相应扭曲区域重叠。 导线可以平行于存储器件字线延伸，并且可以提供电源接地和/或信号线。

    Apparatus and method for signal bus line layout in semiconductor device
    3.
    发明授权
    Apparatus and method for signal bus line layout in semiconductor device 失效
    半导体器件中信号总线布线的装置和方法

    公开(公告)号：US07566589B2

    公开(公告)日：2009-07-28

    申请号：US11809593

    申请日：2007-06-01

    申请人： Chang-Ho Lee ,  Jong-Hyun Choi

    发明人： Chang-Ho Lee ,  Jong-Hyun Choi

    IPC分类号： H01L21/50

    CPC分类号： H01L23/5286 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/14

    摘要： A device and method for layout and fabrication of power supply bus lines in an integrated circuit such as a memory circuit are described. In accordance with the present invention, power bus lines and bonding pads of the circuit are not necessarily formed in both edge regions and center regions of the device. The bonding pads are formed in the region according to the package being used, and the power bus lines are formed in the other region. This is accomplished by forming the bonding pads over landing pads. Landing pads are formed in both the center region and the edge region under the top surface of the device. If the device is to be packaged in an edge pad configuration, the bonding pads are formed over the landing pads in the edge region, and power supply bus lines can be formed over the landing pads in the center region. Similarly, if the device is to be packaged in a center pad configuration, the bonding pads are formed over the landing pads in the center region, and the power supply bus lines can be formed over the landing pads in the edge region.

    摘要翻译： 描述了诸如存储器电路的集成电路中的电源总线布线和制造的装置和方法。 根据本发明，电路的电源总线线路和接合焊盘不一定形成在器件的两个边缘区域和中心区域中。 接合焊盘形成在根据使用的封装的区域中，并且电力总线线路形成在另一区域中。 这通过在着陆垫上形成接合垫来实现。 着陆垫形成在装置的上表面下方的中心区域和边缘区域中。 如果将该器件封装在边缘焊盘配置中，则焊接区形成在边缘区域的着陆焊盘之上，并且电源总线可以形成在中心区域的着陆焊盘上。 类似地，如果要将器件封装在中心焊盘结构中，则接合焊盘形成在中心区域的着陆焊盘之上，并且电源总线可以形成在边缘区域的着陆焊盘上。

    Apparatus and method for signal bus line layout in semiconductor device
    4.
    发明授权
    Apparatus and method for signal bus line layout in semiconductor device 失效

    公开(公告)号：US07245027B2

    公开(公告)日：2007-07-17

    申请号：US10823858

    申请日：2004-04-14

    申请人： Chang-Ho Lee ,  Jong-Hyun Choi

    发明人： Chang-Ho Lee ,  Jong-Hyun Choi

    IPC分类号： H01L23/48

    CPC分类号： H01L23/5286 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/14

    摘要： A device and method for layout and fabrication of power supply bus lines in an integrated circuit such as a memory circuit are described. In accordance with the present invention, power bus lines and bonding pads of the circuit are not necessarily formed in both edge regions and center regions of the device. The bonding pads are formed in the region according to the package being used, and the power bus lines are formed in the other region. This is accomplished by forming the bonding pads over landing pads. Landing pads are formed in both the center region and the edge region under the top surface of the device. If the device is to be packaged in an edge pad configuration, the bonding pads are formed over the landing pads in the edge region, and power supply bus lines can be formed over the landing pads in the center region. Similarly, if the device is to be packaged in a center pad configuration, the bonding pads are formed over the landing pads in the center region, and the power supply bus lines can be formed over the landing pads in the edge region. The bonding pads are connected to the landing pads by conductive vias. Because the power bus lines are not formed in the same region as bonding pads, they can occupy a relatively large portion of the region in which they are formed. That is, they can be made much larger than they would be using the conventional approach in which both bonding pads and power bus lines are formed in the same region. As a result, the power noise drawbacks of the conventional approach are eliminated.

    Apparatus and method for signal bus line layout in semiconductor device
    5.
    发明申请
    Apparatus and method for signal bus line layout in semiconductor device 失效
    半导体器件中信号总线布线的装置和方法

    公开(公告)号：US20070238223A1

    公开(公告)日：2007-10-11

    申请号：US11809593

    申请日：2007-06-01

    申请人： Chang-Ho Lee ,  Jong-Hyun Choi

    发明人： Chang-Ho Lee ,  Jong-Hyun Choi

    IPC分类号： H01L21/00

    CPC分类号： H01L23/5286 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/14

    摘要： A device and method for layout and fabrication of power supply bus lines in an integrated circuit such as a memory circuit are described. In accordance with the present invention, power bus lines and bonding pads of the circuit are not necessarily formed in both edge regions and center regions of the device. The bonding pads are formed in the region according to the package being used, and the power bus lines are formed in the other region. This is accomplished by forming the bonding pads over landing pads. Landing pads are formed in both the center region and the edge region under the top surface of the device. If the device is to be packaged in an edge pad configuration, the bonding pads are formed over the landing pads in the edge region, and power supply bus lines can be formed over the landing pads in the center region. Similarly, if the device is to be packaged in a center pad configuration, the bonding pads are formed over the landing pads in the center region, and the power supply bus lines can be formed over the landing pads in the edge region. The bonding pads are connected to the landing pads by conductive vias. Because the power bus lines are not formed in the same region as bonding pads, they can occupy a relatively large portion of the region in which they are formed. That is, they can be made much larger than they would be using the conventional approach in which both bonding pads and power bus lines are formed in the same region. As a result, the power noise drawbacks of the conventional approach are eliminated.

    摘要翻译： 描述了诸如存储器电路的集成电路中的电源总线布线和制造的装置和方法。 根据本发明，电路的电源总线线路和接合焊盘不一定形成在器件的两个边缘区域和中心区域中。 接合焊盘形成在根据使用的封装的区域中，并且电力总线线路形成在另一区域中。 这通过在着陆垫上形成接合垫来实现。 着陆垫形成在装置的上表面下方的中心区域和边缘区域中。 如果将该器件封装在边缘焊盘配置中，则焊接区形成在边缘区域的着陆焊盘之上，并且电源总线可以形成在中心区域的着陆焊盘上。 类似地，如果要将器件封装在中心焊盘结构中，则接合焊盘形成在中心区域的着陆焊盘之上，并且电源总线可以形成在边缘区域的着陆焊盘上。 接合焊盘通过导电通孔连接到着陆焊盘。 由于电力总线线路不形成在与接合焊盘相同的区域中，所以它们可以占据其形成区域的较大部分。 也就是说，它们可以比使用在相同区域中形成接合焊盘和电力总线线路的常规方法大得多。 结果，消除了常规方法的功率噪声缺点。

    Organic light emitting diode display
    7.
    发明授权
    Organic light emitting diode display 有权
    有机发光二极管显示

    公开(公告)号：US09070645B2

    公开(公告)日：2015-06-30

    申请号：US12929996

    申请日：2011-03-01

    申请人： Hee-Joo Ko ,  Chang-Ho Lee ,  Il Soo Oh ,  Se-Jin Cho ,  Hyung-Jun Song ,  Jin-Young Yun ,  Jong-Hyuk Lee

    发明人： Hee-Joo Ko ,  Chang-Ho Lee ,  Il Soo Oh ,  Se-Jin Cho ,  Hyung-Jun Song ,  Jin-Young Yun ,  Jong-Hyuk Lee

    IPC分类号： H01L51/54 ,  H01L27/32 ,  H01L51/50

    CPC分类号： H01L27/3248 ,  H01L51/5088 ,  H01L51/5092

    摘要： An organic light emitting diode (OLED) display including a substrate main body; a thin film transistor on the substrate main body; and an organic light emitting diode including a transparent electrode connected with the thin film transistor and being capable of injecting electrons, an organic emission layer on the transparent electrode, and a reflective electrode on the organic emission layer and being capable of injecting holes, wherein the organic emission layer includes an electron injection unit on the transparent electrode, the electron injection unit including an electron injection metal layer, an electron injection layer, and an electron injection dipole layer, and a light emitting unit on the electron injection unit.

    摘要翻译： 一种有机发光二极管（OLED）显示器，包括基板主体; 在基板主体上的薄膜晶体管; 以及有机发光二极管，包括与薄膜晶体管连接的能够注入电子的透明电极，透明电极上的有机发射层和有机发射层上的反射电极，并且能够注入空穴，其中， 有机发光层包括在透明电极上的电子注入单元，电子注入单元包括电子注入金属层，电子注入层和电子注入偶极子层以及电子注入单元上的发光单元。