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13 条记录 (耗时 0.028 秒)

    Shallow trench isolation using non-conformal dielectric and planarizatrion
    7.
    发明授权
    Shallow trench isolation using non-conformal dielectric and planarizatrion 有权
    使用非保形介质和平面化的浅沟槽隔离

    公开(公告)号：US06541349B2

    公开(公告)日：2003-04-01

    申请号：US09764674

    申请日：2001-01-18

    申请人： Senthilkumar Arthanari ,  Shaw-Ning Mei ,  Edward J. Vishnesky

    发明人： Senthilkumar Arthanari ,  Shaw-Ning Mei ,  Edward J. Vishnesky

    IPC分类号： H01L2176

    CPC分类号： H01L21/76229

    摘要： A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. The upper regions are covered by a masking layer of nitride having a predetermined thickness. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to a thickness terminating within that of the thickness of the nitride layer. The raised regions of the filler material are then selectively removed in a single planarizing step without removing the filler material in the lowered regions using a fixed abrasive hard polishing pad, as opposed to an abrasive slurry.

    摘要翻译： 提供了一种用于平坦化诸如半导体衬底上的浅沟槽隔离区域的结构的方法。 设置有具有基本垂直和水平表面的升高和降低区域的半导体衬底。 降低的区域可以对应于沟槽区域。 上部区域由具有预定厚度的氮化物掩蔽层覆盖。 诸如非保形高密度等离子体氧化物的填充材料可以沉积在水平表面上，其厚度终止于氮化物层厚度的厚度。 然后在单个平面化步骤中选择性地除去填充材料的凸起区域，而不用磨料浆料使用固定的研磨硬质抛光垫去除降低区域中的填料。

    Flash memory structure with floating gate in vertical trench
    8.
    发明授权
    Flash memory structure with floating gate in vertical trench 有权
    闪存结构，浮动栅极在垂直沟槽中

    公开(公告)号：US6130453A

    公开(公告)日：2000-10-10

    申请号：US225055

    申请日：1999-01-04

    申请人： Shaw-Ning Mei ,  Edward J. Vishnesky

    发明人： Shaw-Ning Mei ,  Edward J. Vishnesky

    IPC分类号： H01L21/336 ,  H01L21/8246 ,  H01L29/423 ,  H01L29/788

    CPC分类号： H01L29/42336 ,  H01L27/11293 ,  H01L29/66825 ,  H01L29/7885

    摘要： A flash memory cell comprises a substrate having a trench formed below the substrate surface, a vertical bit line or auxiliary gate deposited in the trench below the surface, a drain region formed in the substrate below the bit line, and a split floating gate deposited in the trench below the surface to a depth less than the vertical bit line. The floating gate includes a first vertical portion on one side of the bit line and a second vertical portion on another side of the bit line opposite the first vertical portion, with each portion of the gate being accessed by the bit line. The memory cell further includes a source region formed below the surface spaced apart from and adjacent each of the floating gate portions and a word line or control gate extending over the substrate, bit line and floating gate portions. The vertical bit line and split floating gate portions extend from the substrate surface to the bottom of the trench, and adjacent portions of the bit line and the floating gate portions extend above the substrate surface at substantially the same height.

    摘要翻译： 闪存单元包括具有形成在衬底表面下方的沟槽的衬底，沉积在表面下方的沟槽中的垂直位线或辅助栅极，形成在位线下方的衬底中的漏极区域和沉积在 表面下方的沟槽深度小于垂直位线。 浮动栅极包括在位线的一侧上的第一垂直部分和位于与第一垂直部分相对的位线的另一侧上的第二垂直部分，栅极的每个部分被位线访问。 存储单元还包括形成在与每个浮动栅极部分间隔开并相邻的表面下方的源极区域，以及在衬底，位线和浮动栅极部分上延伸的字线或控制栅极。 垂直位线和分离的浮动栅极部分从衬底表面延伸到沟槽的底部，并且位线和浮动栅极部分的相邻部分在基本相同的高度处在衬底表面上方延伸。

    Low cost shallow trench isolation using non-conformal dielectric material
    9.
    发明授权
    Low cost shallow trench isolation using non-conformal dielectric material 失效
    使用非保形介质材料的低成本浅沟槽隔离

    公开(公告)号：US06270353B1

    公开(公告)日：2001-08-07

    申请号：US09326925

    申请日：1999-06-07

    申请人： John W. Andrews ,  Bao T. Hwang ,  Howard S. Landis ,  Shaw-Ning Mei ,  James M. Tyler ,  Edward J. Vishnesky

    发明人： John W. Andrews ,  Bao T. Hwang ,  Howard S. Landis ,  Shaw-Ning Mei ,  James M. Tyler ,  Edward J. Vishnesky

    IPC分类号： H01L2176

    CPC分类号： H01L21/76229

    摘要： A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to at least a thickness equal to a predetermined height so as to provide raised and lowered regions of the filler material. The raised regions of the filler material may then be selectively removed without removing the filler material in the lowered regions.

    摘要翻译： 提供了一种用于平坦化诸如半导体衬底上的浅沟槽隔离区域的结构的方法。 设置有具有基本垂直和水平表面的升高和降低区域的半导体衬底。 降低的区域可以对应于沟槽区域。 诸如非保形高密度等离子体氧化物的填充材料可以在水平表面上沉积至至少等于预定高度的厚度，以便提供填充材料的升高和降低的区域。 然后可以选择性地去除填充材料的凸起区域，而不去除降低区域中的填充材料。

    Self protective decoupling capacitor structure
    10.
    发明授权
    Self protective decoupling capacitor structure 失效
    自保护去耦电容器结构

    公开(公告)号：US5394294A

    公开(公告)日：1995-02-28

    申请号：US992185

    申请日：1992-12-17

    申请人： Shaw-Ning Mei ,  Dominic J. Schepis ,  Andrie S. Yapsir

    发明人： Shaw-Ning Mei ,  Dominic J. Schepis ,  Andrie S. Yapsir

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/08 ,  H01G1/11

    CPC分类号： H01L27/0805 ,  H01L27/0218

    摘要： An integrated circuit decoupling capacitor is divided into a plurality of discrete segments. The segments are connected electrically in parallel and are redundant to an extent that if one segment (or if desired more than one segment) fails, the remaining segments have sufficient capacitance to provide the required decoupling function. Each decoupling capacitor segment has a fuse connected in series with it. The fuse opens in response to a fault in a decoupling capacitor segment that would otherwise cause that segment to short the power supply to ground.

    摘要翻译： 集成电路去耦电容器被分成多个离散段。 这些段并联电连接并且是冗余的，如果一个段（或者如果期望的多于一个段）失败，则剩余段具有足够的电容以提供所需的解耦功能。 每个去耦电容器段具有与其串联的保险丝。 保险丝响应于去耦电容器段中的故障而断开，否则将导致该段将电源短路到地。