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公开(公告)号：US5331199A
公开(公告)日：1994-07-19
申请号：US046709
申请日：1993-04-16
IPC分类号： H01L21/225 , H01L21/285 , H01L21/331 , H01L29/06 , H01L29/10 , H01L29/72 , H01L29/04
CPC分类号： H01L29/66287 , H01L21/2257 , H01L21/28525 , H01L29/0649 , H01L29/1004
摘要： A vertical bipolar transistor is constructed with reduced step height by codeposition of a polysilicon base contact member and an epitaxial device layer, thereby placing the base contact below the device surface, and by the use of a doped glass layer as a dopant source for the base contact and as a dopant source to provide a continuous conductive path to the base, and as the dielectric separating the base contact from the emitter contact, and as an etch stop when forming the base implantation aperture.
摘要翻译： 通过多晶硅底部接触构件和外延装置层的共沉积，构建具有降低的台阶高度的垂直双极晶体管，从而将基极接触放置在器件表面下方，并且通过使用掺杂的玻璃层作为基极的掺杂剂源 接触和作为掺杂剂源以提供到基底的连续导电路径，以及作为将基极接触与发射极接触分离的介质，以及当形成基极注入孔时作为蚀刻停止。
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公开(公告)号：US5234846A
公开(公告)日：1993-08-10
申请号：US876597
申请日：1992-04-30
IPC分类号： H01L21/225 , H01L21/285 , H01L21/331 , H01L29/06 , H01L29/10
CPC分类号： H01L29/66287 , H01L21/2257 , H01L21/28525 , H01L29/0649 , H01L29/1004
摘要： A vertical bipolar transistor is constructed with reduced step height by codeposition of a polysilicon base contact member and an epitaxial device layer, thereby placing the base contact below the device surface, and by the use of a doped glass layer as a dopant source for the base contact and as a dopant source to provide a continuous conductive path to the base, and as the dielectric separating the base contact from the emitter contact, and as an etch stop when forming the base implantation aperture.
摘要翻译： 通过多晶硅底部接触构件和外延装置层的共沉积，构建具有降低的台阶高度的垂直双极晶体管，从而将基极接触放置在器件表面下方，并且通过使用掺杂的玻璃层作为基极的掺杂剂源 接触和作为掺杂剂源以提供到基底的连续导电路径，以及作为将基极接触与发射极接触分离的介质，以及当形成基极注入孔时作为蚀刻停止。
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3.发明授权Method of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuits 失效用于BiCMOS集成电路的氧化物半导体器件结构上形成硅的方法
公开(公告)号：US5484738A
公开(公告)日：1996-01-16
申请号：US396985
申请日：1995-03-01
IPC分类号： H01L21/76 , H01L21/02 , H01L21/762 , H01L21/8249 , H01L27/06 , H01L27/12 , H01L29/786 , H01L21/265
CPC分类号： H01L21/8249 , H01L21/76251 , H01L27/0623 , Y10S148/01 , Y10S148/011 , Y10S148/012 , Y10S148/05 , Y10S148/151
摘要： A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.
摘要翻译： 首先形成在体硅晶片中的具有阶梯式隔离沟槽和子层互连的键合SOI晶片。 在这些工艺步骤完成之后，在本体硅晶片的平坦化上表面上形成薄多晶硅层。 然后将该薄多晶硅层结合到单独晶片的表面上的氧化物层，以形成键合的氧化硅结构。 整个组件实际上是倒置的，并且本体硅晶片的下表面被移除到最深沟槽台阶的底部。 在这种键合的SOI结构中，沟槽之间的区域是深的并且适合于双极器件制造，而沟槽台阶形成适于制造CMOS器件的浅区域。
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4.发明授权Advanced silicon on oxide semiconductor device structure for BiCMOS integrated circuit 失效用于BiCMOS集成电路的先进硅氧化物半导体器件结构
公开(公告)号：US5521399A
公开(公告)日：1996-05-28
申请号：US242992
申请日：1994-05-16
IPC分类号： H01L21/76 , H01L21/02 , H01L21/762 , H01L21/8249 , H01L27/06 , H01L27/12 , H01L29/786 , H01L27/01 , H01L27/04
CPC分类号： H01L21/8249 , H01L21/76251 , H01L27/0623 , Y10S148/01 , Y10S148/011 , Y10S148/012 , Y10S148/05 , Y10S148/151
摘要： A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.
摘要翻译： 首先形成在体硅晶片中的具有阶梯式隔离沟槽和子层互连的键合SOI晶片。 在这些工艺步骤完成之后，在本体硅晶片的平坦化上表面上形成薄多晶硅层。 然后将该薄多晶硅层结合到单独晶片的表面上的氧化物层，以形成键合的氧化硅结构。 整个组件实际上是倒置的，并且本体硅晶片的下表面被移除到最深沟槽台阶的底部。 在这种键合的SOI结构中，沟槽之间的区域是深的并且适合于双极器件制造，而沟槽台阶形成适于制造CMOS器件的浅区域。
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公开(公告)号：US5229322A
公开(公告)日：1993-07-20
申请号：US804228
申请日：1991-12-05
申请人： Shao-Fu S. Chu , Kyong-Min Kim , Shaw-Ning Mei , Mary J. Saccamango , Donald R. Vigliotti , Robert J. von Gutfeld
发明人： Shao-Fu S. Chu , Kyong-Min Kim , Shaw-Ning Mei , Mary J. Saccamango , Donald R. Vigliotti , Robert J. von Gutfeld
CPC分类号： H01L21/743 , Y10S117/904 , Y10S148/09
摘要： An inexpensive and reliable technique for forming connections to a substrate or buried layer of a semiconductor structure employs a laser to melt a small, selected region of a lightly doped layer and a highly doped underlying layer. Extremely rapid diffusion of impurities and mixing of materials within the liquid phase of the melt quickly creates a uniformly doped conductive region when the melt is allowed to recrystallize.
摘要翻译： 用于形成与半导体结构的衬底或掩埋层的连接的便宜且可靠的技术使用激光来熔化轻掺杂层和高度掺杂的下层的小的选定区域。 当熔体被允许重结晶时，杂质的极快速扩散和材料在熔体液相内的混合会快速产生均匀掺杂的导电区域。
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6.发明授权Image reversal process for self-aligned implants in planar epitaxial-base bipolar transistors 失效在平面外延基极双极晶体管中自对准植入物的图像反转过程
公开(公告)号：US5266505A
公开(公告)日：1993-11-30
申请号：US994743
申请日：1992-12-22
IPC分类号： H01L21/331 , H01L21/265 , H01L29/70
CPC分类号： H01L29/66287 , Y10S148/072
摘要： An image reversal process for self-aligned implants in which a mask opening and plug in the opening are used to enable one implant in the mask opening, another self-aligned implant in the region surrounding the opening, and a self-aligned electrode to be formed in the opening.
摘要翻译： 用于自对准植入物的图像反转过程，其中开口中的掩模开口和插塞用于使掩模开口中的一个植入物，围绕开口的区域中的另一个自对准植入物，以及自对准电极 形成在开口。
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7.发明授权
公开(公告)号：US5015594A
公开(公告)日：1991-05-14
申请号：US261952
申请日：1988-10-24
申请人： Shao-Fu S. Chu , San-Mei Ku , Russell C. Lange , Joseph F. Shephard , Paul J. Tsang , Wen-Yuan Wang
发明人： Shao-Fu S. Chu , San-Mei Ku , Russell C. Lange , Joseph F. Shephard , Paul J. Tsang , Wen-Yuan Wang
IPC分类号： H01L29/73 , H01L21/331 , H01L21/60 , H01L21/8249 , H01L27/06 , H01L29/732
CPC分类号： H01L21/76897 , H01L21/8249 , Y10S148/009
摘要： A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall.In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls. The second contact is thus self-aligned with the first and second doped regions and the first device contact.The method of the present invention can be utilized to fabricate bipolar transistors, insulated gate transistors, and BICMOS logic including both types of transistors. It can further be used to fabricate any other type of semiconductor device which utilizes the self-aligned, closely spaced device regions and contacts of the present invention.
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