公开(公告)号：US07457897B1

公开(公告)日：2008-11-25

申请号：US10803597

申请日：2004-03-17

申请人： Charles C. Lee ,  Sun-Teck See ,  Horng-Yee Chou ,  I-Pieng Peter Kao

发明人： Charles C. Lee ,  Sun-Teck See ,  Horng-Yee Chou ,  I-Pieng Peter Kao

IPC分类号： G06F3/00 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F13/1684 ,  G11C13/0004 ,  G11C16/102 ,  G11C2216/30

摘要： A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.

摘要翻译： 兼容PCI Express的闪存设备可以包括一个或多个闪存模块，控制器和ExpressCard接口。 控制器可以有利地提供PCI Express功能以及闪速存储器操作，例如， 使用ExpressCard接口进行写入，读取或擦除。 PIO接口包括向闪存设备发送第一和第二存储器请求包。 第一存储器请求分组包括为所需操作准备闪存设备的命令字设置。 如果需要，第二存储器请求分组触发操作并且包括数据有效载荷。 DMA接口包括将第二存储器请求从闪存设备发送到主机，从而触发主机释放用于DMA操作的系统总线。

公开(公告)号：US20090049222A1

公开(公告)日：2009-02-19

申请号：US12254428

申请日：2008-10-20

申请人： Charles C. Lee ,  Sun-Teck See ,  Horng-Yee Chou ,  I-pieng Peter Kao

发明人： Charles C. Lee ,  Sun-Teck See ,  Horng-Yee Chou ,  I-pieng Peter Kao

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F13/1684 ,  G11C13/0004 ,  G11C16/102 ,  G11C2216/30

摘要： A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.

摘要翻译： 兼容PCI Express的闪存设备可以包括一个或多个闪存模块，控制器和ExpressCard接口。 控制器可以有利地提供PCI Express功能以及闪速存储器操作，例如， 使用ExpressCard接口进行写入，读取或擦除。 PIO接口包括向闪存设备发送第一和第二存储器请求包。 第一存储器请求分组包括为所需操作准备闪存设备的命令字设置。 如果需要，第二存储器请求分组触发操作并且包括数据有效载荷。 DMA接口包括将第二存储器请求从闪存设备发送到主机，从而触发主机释放用于DMA操作的系统总线。

公开(公告)号：US07849242B2

公开(公告)日：2010-12-07

申请号：US12254428

申请日：2008-10-20

申请人： Charles C. Lee ,  Sun-Teck See ,  Horng-Yee Chou ,  I-pieng Peter Kao

发明人： Charles C. Lee ,  Sun-Teck See ,  Horng-Yee Chou ,  I-pieng Peter Kao

IPC分类号： G06F3/00 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F13/1684 ,  G11C13/0004 ,  G11C16/102 ,  G11C2216/30

摘要： A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.

摘要翻译： 兼容PCI Express的闪存设备可以包括一个或多个闪存模块，控制器和ExpressCard接口。 控制器可以有利地提供PCI Express功能以及闪速存储器操作，例如， 使用ExpressCard接口进行写入，读取或擦除。 PIO接口包括向闪存设备发送第一和第二存储器请求包。 第一存储器请求分组包括为所需操作准备闪存设备的命令字设置。 如果需要，第二存储器请求分组触发操作并且包括数据有效载荷。 DMA接口包括将第二存储器请求从闪存设备发送到主机，从而触发主机释放用于DMA操作的系统总线。

公开(公告)号：US07243185B2

公开(公告)日：2007-07-10

申请号：US10818653

申请日：2004-04-05

申请人： Sun-Teck See ,  Tzu-Yih Chu ,  Horng-Yee Chou ,  Charles C. Lee

发明人： Sun-Teck See ,  Tzu-Yih Chu ,  Horng-Yee Chou ,  Charles C. Lee

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F12/0804 ,  G06F2212/2022 ,  G11C7/1015 ,  G11C2211/5641

摘要： A multi media card (MMC) is disclosed. The MMC includes a flash controller and at least one flash memory device. The flash controller increases the throughput of the at least one flash memory device to match the speed of a host bus coupled to the MMC. The flash controller increases the throughput by performing one or more of performing a read-ahead memory read operation, performing a write-ahead memory write operation, increasing the size of a page register of the at least one flash memory device, increasing the width of a memory data bus, performing a dual-channel concurrent memory read operation, performing a dual-channel concurrent memory write operation, performing a write-cache memory write operation, and any combination thereof.

摘要翻译： 公开了一种多媒体卡（MMC）。 MMC包括闪存控制器和至少一个闪存设备。 闪存控制器增加至少一个闪存设备的吞吐量以匹配耦合到MMC的主机总线的速度。 闪存控制器通过执行执行预读存储器读取操作，执行写入预先存储器写入操作，增加至少一个闪速存储器件的页面寄存器的大小中的一个或多个来增加吞吐量， 存储器数据总线，执行双通道并行存储器读取操作，执行双通道并行存储器写入操作，执行写入 - 高速缓冲存储器写入操作及其任何组合。

公开(公告)号：US07126873B2

公开(公告)日：2006-10-24

申请号：US10882005

申请日：2004-06-29

申请人： Sun-Teck See ,  Horng-Yee Chou ,  Charles C. Lee

发明人： Sun-Teck See ,  Horng-Yee Chou ,  Charles C. Lee

IPC分类号： G11C8/00 ,  G11C7/10 ,  G11C16/04 ,  G06F12/02 ,  G06F12/06

CPC分类号： G11C16/02

摘要： Through the use of an allocation logic unit with a Flash controller, a single primary chip enable is de-multiplexed into a multiple secondary chip enables for multiple Flash memory dies or chips. In so doing, Flash storage device capacity is greatly expanded. In a first aspect, a memory package includes a plurality of memories; and an allocation logic unit coupled to the plurality of memories for receiving a single chip enable signal. The allocation logic unit de-multiplexes the single chip enable signal to a plurality of chip enable signals. Each of the plurality of chip enable signals access to one of the plurality of memories.In a second aspect, a printed circuit board (PCB) includes a Flash controller for providing at least one primary chip enable signal. The PCB also includes a plurality of Flash memory chips and at least one allocation logic unit coupled to at least a portion of the plurality of Flash memory chips and the Flash controller. The allocation logic unit receives the at least one chip enable signal and de-multiplexes the at least one chip enable signal to a plurality of secondary chip enable signals. Each of the plurality of chip enable signals controls access to one of the Flash memory chips.

摘要翻译： 通过使用具有闪存控制器的分配逻辑单元，单个主芯片使能被解复用到多个次级芯片中，使得能够用于多个闪存芯片或芯片。 这样做，Flash存储设备容量大大扩大。 在第一方面，一种存储器包括多个存储器; 以及耦合到所述多个存储器以用于接收单个芯片使能信号的分配逻辑单元。 分配逻辑单元将单芯片使能信号解复用到多个芯片使能信号。 多个芯片使能信号中的每一个访问多个存储器中的一个。 在第二方面，印刷电路板（PCB）包括用于提供至少一个主芯片使能信号的闪光控制器。 PCB还包括多个闪存芯片和耦合到多个闪存芯片和闪存控制器的至少一部分的至少一个分配逻辑单元。 所述分配逻辑单元接收所述至少一个芯片使能信号，并且将所述至少一个芯片使能信号解复用到多个次级芯片使能信号。 多个芯片使能信号中的每一个控制对闪存芯片之一的访问。

公开(公告)号：US07103684B2

公开(公告)日：2006-09-05

申请号：US10707277

申请日：2003-12-02

申请人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See ,  Charles C. Lee

发明人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See ,  Charles C. Lee

IPC分类号： G06F3/00 ,  G06F13/28 ,  G06F13/12

CPC分类号： G06F13/28 ,  G06F3/0679 ,  Y02D10/14

摘要： A Universal-Serial-Bus (USB) single-chip flash device contains a USB flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. USB packets from a host USB bus are read by a serial engine on the USB flash microcontroller. Various routines that execute on a CPU in the USB flash microcontroller are activated in response to commands in the USB packets. A flash-memory controller in the USB flash microcontroller transfers data from the serial engine to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

摘要翻译： 通用串行总线（USB）单芯片闪存器件包含一个USB闪存单片机和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。 来自主机USB总线的USB数据包由USB闪存单片机上的串行引擎读取。 响应于USB数据包中的命令，激活在USB闪存单片机中的CPU上执行的各种例程。 USB闪存单片机中的闪存控制器将数据从串行引擎传输到闪存大容量存储块进行存储。 不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。 在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

公开(公告)号：US07690030B1

公开(公告)日：2010-03-30

申请号：US11458987

申请日：2006-07-20

申请人： Abraham C. Ma ,  Sun-Teck See ,  Charles C. Lee ,  Edward W. Lee ,  Ming-Shiang Shen

发明人： Abraham C. Ma ,  Sun-Teck See ,  Charles C. Lee ,  Edward W. Lee ,  Ming-Shiang Shen

IPC分类号： G06F7/04

CPC分类号： G06F12/1416 ,  G06F21/32 ,  G06F21/34 ,  G06F21/78 ,  G06K19/07 ,  G06K19/07354

摘要： An electronic data flash card with fingerprint capability is accessible by an host computer, and includes a processing unit connected to a flash memory device that stores a data file and reference fingerprint data of a person authorized to access the data file, a fingerprint sensor for scanning the fingerprint of a user and for generating input fingerprint data that can be compared with the stored reference fingerprint data, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer.

摘要翻译： 具有指纹能力的电子数据闪存卡可由主机访问，并且包括连接到闪存设备的处理单元，该闪存设备存储被授权访问数据文件的人员的数据文件和参考指纹数据，用于扫描的指纹传感器 用户的指纹和用于生成可以与存储的参考指纹数据进行比较的输入指纹数据，以及激活以便建立与主计算机的通信的输入 - 输出接口电路。 在一个实施例中，电子数据闪存卡使用USB输入/输出接口电路与主计算机进行通信。

公开(公告)号：US07673080B1

公开(公告)日：2010-03-02

申请号：US10917576

申请日：2004-08-13

申请人： I-Kang Yu ,  Horng-Yee Chou ,  Szu-Kuang Chou ,  Charles C. Lee

发明人： I-Kang Yu ,  Horng-Yee Chou ,  Szu-Kuang Chou ,  Charles C. Lee

IPC分类号： G06F13/12 ,  G06F13/00

CPC分类号： G06F13/387 ,  G06F13/385 ,  G06K19/07732 ,  G06K19/07733 ,  Y02D10/14 ,  Y02D10/151

摘要： A flash memory card includes a differential datapath that enables communications between the flash memory card and a host device to be performed using differential signals. The differential datapath can translate between the differential signals and card-specific signals that control read/write operations to the memory array of the flash memory card. The card-specific signals can be standard MultiMediaCard, Secure-Digital card, Memory Stick, or CompactFlash card signals, among others. A host device that provides differential data transfer capability can include a similar differential datapath. By using differential data transfer rather than conventional clocked data transfer, overall data bandwidth between a flash memory card and a host device can be significantly increased, while simultaneously decreasing power consumption and pin requirements.

摘要翻译： 闪存卡包括差分数据路径，其使得能够使用差分信号执行闪存卡与主机设备之间的通信。 差分数据路径可以在差分信号和控制对闪存卡的存储器阵列的读/写操作的卡特定信号之间进行转换。 特定于卡的信号可以是标准的多媒体卡，安全数字卡，记忆棒或CompactFlash卡信号。 提供差分数据传输能力的主机设备可以包括类似的差分数据路径。 通过使用差分数据传输而不是传统的时钟数据传输，闪存卡和主机设备之间的总体数据带宽可以显着增加，同时降低功耗和引脚要求。

公开(公告)号：US07657692B2

公开(公告)日：2010-02-02

申请号：US11926636

申请日：2007-10-29

申请人： Charles C. Lee ,  David Q. Chow ,  Abraham C. Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

发明人： Charles C. Lee ,  David Q. Chow ,  Abraham C. Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

IPC分类号： G06F13/00

CPC分类号： G06F13/28 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An extended universal-serial bus (EUSB) bridge to a host computer can have peripheral component interconnect express (PCIE) protocol layers on one side of the bridge, and EUSB layers on the other side of the bridge, with a high-level bridging converter module connecting the upper layers. The PCIE physical, data-link, and transport layers may be eliminated by integrating the bridge with an I/O controller. PCIE requests and data payloads are directly sent to the bridge, rather than low-level PCIE physical signals. The PCIE data payloads are converted to EUSB data payloads by a high-level direct bridging converter module. Then the EUSB data payloads are passed down to an EUSB transaction layer, an EUSB data-link layer, and an EUSB physical layer which drives and senses physical electrical signals on both differential pairs of the EUSB bus.

摘要翻译： 到主机的扩展通用串行总线（EUSB）桥可以在桥的一侧具有外围组件互连快速（PCIE）协议层，并且在桥的另一侧可以具有高级桥接转换器 模块连接上层。 可以通过将桥与I / O控制器集成来消除PCIE物理，数据链路和传输层。 PCIE请求和数据有效载荷直接发送到桥，而不是低级PCIE物理信号。 PCIE数据有效载荷通过高级直接桥接转换器模块转换为EUSB数据有效载荷。 然后，EUSB数据有效载荷被传递到EUSB事务层，EUSB数据链路层和EUSB物理层，其在EUSB总线的两个差分对上驱动和感测物理电信号。

公开(公告)号：US07069369B2

公开(公告)日：2006-06-27

申请号：US10708634

申请日：2004-03-16

申请人： Horng-Yee Chou ,  Szu-Kuang Chou ,  Charles C. Lee

发明人： Horng-Yee Chou ,  Szu-Kuang Chou ,  Charles C. Lee

IPC分类号： G06F13/00

CPC分类号： G06F13/385 ,  G06K19/07732 ,  G06K19/07733 ,  H01R13/26

摘要： An extended Secure-Digital (SD) card has a second interface that uses some of the SD-interface lines. The SD card's mechanical and electrical card-interface is used, but 2 or 4 signals in the SD interface are multiplexed for use by the second interface. The second interface can have a single differential pair of serial-data lines to perform Universal-Serial-Bus (USB) transfers, or two pairs of differential data lines for Serial-Advanced-Technology-Attachment (SATA), Peripheral Component Interconnect Express (PCIE), or IEEE 1394 transfers. A card-detection routine on a host can initially use the SD interface to detect extended capabilities and command the card to switch to using the second interface. The extended SD card can communicate with legacy SD hosts using just the SD interface, and extended SD hosts can read legacy SD cards using just the SD interface, or extended SD cards using the second interface. MultiMediaCard and Memory Stick are alternatives.

摘要翻译： 扩展的安全数字（SD）卡具有使用一些SD接口线路的第二接口。 使用SD卡的机电卡接口，SD接口中的2或4个信号被复用以供第二个接口使用。 第二个接口可以具有单个差分对的串行数据线来执行通用串行总线（USB）传输，或两对差分数据线用于串行高级技术附件（SATA），外围组件互连Express（Express） PCIE）或IEEE 1394传输。 主机上的卡检测程序最初可以使用SD接口来检测扩展功能，并命令卡切换到使用第二个接口。 扩展SD卡可以使用SD接口与传统SD主机进行通信，扩展SD主机可以使用SD接口读取旧SD卡，也可以使用第二个接口读取扩展SD卡。 多媒体卡和记忆棒是替代品。