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    Differential data transfer for flash memory card
    1.
    发明授权
    Differential data transfer for flash memory card 失效
    闪存卡差分数据传输

    公开(公告)号：US07673080B1

    公开(公告)日：2010-03-02

    申请号：US10917576

    申请日：2004-08-13

    申请人： I-Kang Yu ,  Horng-Yee Chou ,  Szu-Kuang Chou ,  Charles C. Lee

    发明人： I-Kang Yu ,  Horng-Yee Chou ,  Szu-Kuang Chou ,  Charles C. Lee

    IPC分类号： G06F13/12 ,  G06F13/00

    CPC分类号： G06F13/387 ,  G06F13/385 ,  G06K19/07732 ,  G06K19/07733 ,  Y02D10/14 ,  Y02D10/151

    摘要： A flash memory card includes a differential datapath that enables communications between the flash memory card and a host device to be performed using differential signals. The differential datapath can translate between the differential signals and card-specific signals that control read/write operations to the memory array of the flash memory card. The card-specific signals can be standard MultiMediaCard, Secure-Digital card, Memory Stick, or CompactFlash card signals, among others. A host device that provides differential data transfer capability can include a similar differential datapath. By using differential data transfer rather than conventional clocked data transfer, overall data bandwidth between a flash memory card and a host device can be significantly increased, while simultaneously decreasing power consumption and pin requirements.

    摘要翻译： 闪存卡包括差分数据路径，其使得能够使用差分信号执行闪存卡与主机设备之间的通信。 差分数据路径可以在差分信号和控制对闪存卡的存储器阵列的读/写操作的卡特定信号之间进行转换。 特定于卡的信号可以是标准的多媒体卡，安全数字卡，记忆棒或CompactFlash卡信号。 提供差分数据传输能力的主机设备可以包括类似的差分数据路径。 通过使用差分数据传输而不是传统的时钟数据传输，闪存卡和主机设备之间的总体数据带宽可以显着增加，同时降低功耗和引脚要求。

    Differential data transfer for flash memory card
    2.
    发明授权
    Differential data transfer for flash memory card 有权
    闪存卡差分数据传输

    公开(公告)号：US07844763B2

    公开(公告)日：2010-11-30

    申请号：US12608842

    申请日：2009-10-29

    申请人： I-Kang Yu ,  Horng-Yee Chou ,  Szu-Kuang Chou ,  Charles C. Lee

    发明人： I-Kang Yu ,  Horng-Yee Chou ,  Szu-Kuang Chou ,  Charles C. Lee

    IPC分类号： G06F13/12 ,  G06F13/00

    CPC分类号： G06F13/387 ,  G06F13/385 ,  G06K19/07732 ,  G06K19/07733 ,  Y02D10/14 ,  Y02D10/151

    摘要： A flash memory card includes a differential datapath that enables communications between the flash memory card and a host device to be performed using differential signals. The differential datapath can translate between the differential signals and card-specific signals that control read/write operations to the memory array of the flash memory card. The card-specific signals can be standard MultimediaCard, Secure-Digital card, Memory Stick, or CompactFlash card signals, among others. A host device that provides differential data transfer capability can include a similar differential datapath. By using differential data transfer rather than conventional clocked data transfer, overall data bandwidth between a flash memory card and a host device can be significantly increased, while simultaneously decreasing power consumption and pin requirements.

    摘要翻译： 闪存卡包括差分数据路径，其使得能够使用差分信号执行闪存卡与主机设备之间的通信。 差分数据路径可以在差分信号和控制对闪存卡的存储器阵列的读/写操作的卡特定信号之间进行转换。 卡特定信号可以是标准的多媒体卡，安全数字卡，记忆棒或CompactFlash卡信号。 提供差分数据传输能力的主机设备可以包括类似的差分数据路径。 通过使用差分数据传输而不是传统的时钟数据传输，闪存卡和主机设备之间的总体数据带宽可以显着增加，同时降低功耗和引脚要求。

    Differential Data Transfer For Flash Memory Card
    3.
    发明申请
    Differential Data Transfer For Flash Memory Card 有权
    闪存卡差分数据传输

    公开(公告)号：US20100049878A1

    公开(公告)日：2010-02-25

    申请号：US12608842

    申请日：2009-10-29

    申请人： I-Kang Yu ,  Horng-Yee Chou ,  Szu-Kuang Chou ,  Charles C. Lee

    发明人： I-Kang Yu ,  Horng-Yee Chou ,  Szu-Kuang Chou ,  Charles C. Lee

    IPC分类号： G06F13/12 ,  G06F12/00 ,  G06F13/00

    CPC分类号： G06F13/387 ,  G06F13/385 ,  G06K19/07732 ,  G06K19/07733 ,  Y02D10/14 ,  Y02D10/151

    摘要： A flash memory card includes a differential datapath that enables communications between the flash memory card and a host device to be performed using differential signals. The differential datapath can translate between the differential signals and card-specific signals that control read/write operations to the memory array of the flash memory card. The card-specific signals can be standard MultimediaCard, Secure-Digital card, Memory Stick, or CompactFlash card signals, among others. A host device that provides differential data transfer capability can include a similar differential datapath. By using differential data transfer rather than conventional clocked data transfer, overall data bandwidth between a flash memory card and a host device can be significantly increased, while simultaneously decreasing power consumption and pin requirements.

    摘要翻译： 闪存卡包括差分数据路径，其使得能够使用差分信号执行闪存卡与主机设备之间的通信。 差分数据路径可以在差分信号和控制对闪存卡的存储器阵列的读/写操作的卡特定信号之间进行转换。 卡特定信号可以是标准的多媒体卡，安全数字卡，记忆棒或CompactFlash卡信号。 提供差分数据传输能力的主机设备可以包括类似的差分数据路径。 通过使用差分数据传输而不是传统的时钟数据传输，闪存卡和主机设备之间的总体数据带宽可以显着增加，同时降低功耗和引脚要求。

    High endurance non-volatile memory devices
    8.
    发明授权
    High endurance non-volatile memory devices 有权
    高耐久性非易失性存储器件

    公开(公告)号：US07953931B2

    公开(公告)日：2011-05-31

    申请号：US12035398

    申请日：2008-02-21

    申请人： I-Kang Yu ,  David Q. Chow ,  Charles C. Lee ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

    发明人： I-Kang Yu ,  David Q. Chow ,  Charles C. Lee ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

    IPC分类号： G06F12/12

    CPC分类号： G06F13/161 ,  G06F12/0246 ,  G06F12/0862 ,  G06F12/123 ,  G06F2212/7203 ,  G11C11/5621 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2211/5641 ,  G11C2211/5643

    摘要： High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

    摘要翻译： 描述了高耐久性非易失性存储器件（NVMD）。 高耐久性NVMD包括I / O接口，NVM控制器，CPU以及易失性存储器子系统和至少一个非易失性存储器（NVM）模块。 易失性存储器缓存子系统被配置为数据高速缓存子系统。 当NVMD适用于主机系统时，至少一个NVM模块被配置为数据存储器。 I / O接口被配置为从主机接收数据缓存子系统的传入数据，并将请求数据从数据缓存子系统发送到主机。 至少一个NVM模块可以包括至少第一和第二类型的NVM。 第一种类型包括SLC闪存，而第二种类型的MLC闪存。 NVM的第一种类型被配置为数据高速缓存子系统和第二类NVM之间的缓冲区。

    MEMORY ADDRESS MANAGEMENT SYSTEMS IN A LARGE CAPACITY MULTI-LEVEL CELL (MLC) BASED FLASH MEMORY DEVICE
    9.
    发明申请
    MEMORY ADDRESS MANAGEMENT SYSTEMS IN A LARGE CAPACITY MULTI-LEVEL CELL (MLC) BASED FLASH MEMORY DEVICE 有权
    基于大容量多级电池（MLC）的闪存存储器件中的存储器地址管理系统

    公开(公告)号：US20110093653A1

    公开(公告)日：2011-04-21

    申请号：US12980591

    申请日：2010-12-29

    申请人： Charles C. Lee ,  I-Kang Yu ,  David Nguyen ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

    发明人： Charles C. Lee ,  I-Kang Yu ,  David Nguyen ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

    IPC分类号： G06F12/00

    CPC分类号： H05K1/182 ,  G06F12/00 ,  H01R13/447 ,  H05K1/181 ,  H05K5/0278 ,  H05K2201/10189 ,  H05K2201/10446 ,  H05K2203/1572

    摘要： Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.

    摘要翻译： 描述了在大容量多级基于单元的闪存设备中管理存储器地址的方法和系统。 根据一个方面，一种闪存设备包括一个使用索引方案来管理逻辑到物理地址相关的处理单元。 闪存被分为N组。 每个集合包括多个条目（即，块）。 对于物理块号和相关联的页面使用信息（以下称为“PLTPPUI”）的N组部分逻辑条目号被存储在基于MLC的闪速存储器的保留区域中。 只有一个N集被加载以寻址相关和页面使用存储器（ACPUM），这是一个有限大小的随机存取存储器（RAM）。 在一个实施例中，静态RAM（SRAM）被实现用于地址相关的快速访问时间。 与数据传输请求一起接收的LSA指示将N组PLTPPUI中的哪一个加载到ACPUM中。

    Electronic data flash card with Reed Solomon error detection and correction capability
    10.
    发明授权
    Electronic data flash card with Reed Solomon error detection and correction capability 失效
    电子数据闪存卡，具有Reed Solomon错误检测和校正功能

    公开(公告)号：US07890846B2

    公开(公告)日：2011-02-15

    申请号：US11739613

    申请日：2007-04-24

    申请人： Charles C. Lee ,  I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

    发明人： Charles C. Lee ,  I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

    IPC分类号： H03M13/00

    CPC分类号： H03M13/1545 ,  G06F11/1068 ,  G06F11/1076 ,  H03M13/153 ,  H03M13/1535 ,  H03M13/6561

    摘要： One embodiment of the present includes a electronic data storage card having a Reed Solomon (RS) decoder having a syndrome calculator block responsive to a page of information, the page being organized into a plurality of data sections and the overhead being organized into a plurality of overhead sections. The syndrome calculator generates a syndrome for each of the data sections. The decoder further includes a root finder block responsive to the calculated syndrome and for generating at least two roots, a polynomial calculator block responsive to the at least two roots and operative to generate at least one error address, identifying a location in the data wherein the error lies, and an error symbol values calculator block coupled to the root finder and the polynomial calculator block and for generating a second error address, identifying a second location in the data wherein the error(s) lie.

    摘要翻译： 本发明的一个实施例包括具有Reed Solomon（RS）解码器的电子数据存储卡，该解码器具有响应于信息页的校正子计算器块，该页被组织成多个数据段，并且开销被组织成多个 架空部分。 综合征计算器为每个数据部分产生综合征。 解码器还包括响应于所计算的校正子并用于生成至少两个根的根取景器块，响应于至少两个根并且可操作地生成至少一个错误地址的多项式计算器块，识别数据中的位置，其中， 并且错误符号值计算器块耦合到根查找器和多项式计算器块，并用于产生第二错误地址，识别错误所在的数据中的第二位置。