公开(公告)号：US5061650A

公开(公告)日：1991-10-29

申请号：US643835

申请日：1991-01-17

申请人： Charles H. Dennison ,  Hiang Chan ,  Yauh-Ching Liu ,  Pierre Fazan ,  Howard E. Rhodes

发明人： Charles H. Dennison ,  Hiang Chan ,  Yauh-Ching Liu ,  Pierre Fazan ,  Howard E. Rhodes

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L28/91 ,  H01L27/10817

摘要： A method is disclosed for forming a capacitor on a semiconductor wafer. A first electrically conductive layer is applied atop the wafer and engages exposed active areas. A first dielectric layer is next applied. The first dielectric and conductive layers are then patterned to define an outline for the lower capacitor plate. A second dielectric layer, having an etch rate which is slower than the first, is then applied and planarized or otherwise etched down to the first dielectric layer. The first dielectric layer is then etched down to the first conductive layer to produce upwardly projecting walls of second dielectric material surrounding the lower capacitor plate outline. A second electrically conductive layer is then applied. It is then anisotropically etched to provide a first electrically conductive wall extending upwardly from the first conductive layer. A third dielectric layer is then applied. The third dielectric layer is then anisotropicallly etched to provide a first dielectric wall extending upwardly from the first conductive layer adjacent the first conductive wall. A third electrically conductive layer is next applied over the first conductive and dielectric walls. It is then anisotropically etched to provide a second electrically conductive wall extending upwardly from the first conductive layer adjacent the first dielectric wall. The first dielectric wall is then etched from the wafer. A capacitor dielectric layer is then applied, followed by a fourth electrically conductive layer to form an upper capacitor plate.

摘要翻译： 公开了一种在半导体晶片上形成电容器的方法。 将第一导电层施加在晶片顶部并接合暴露的有源区。 接下来应用第一电介质层。 然后将第一介电层和导电层图案化以限定下电容器板的轮廓。 然后施加具有比第一介质层慢的蚀刻速率的第二介电层，并将其平坦化或以其它方式蚀刻到第一介电层。 然后将第一电介质层向下蚀刻到第一导电层，以产生围绕较低电容器板轮廓的第二介电材料的向上突出的壁。 然后施加第二导电层。 然后对其进行各向异性蚀刻以提供从第一导电层向上延伸的第一导电壁。 然后施加第三介电层。 然后对第三电介质层进行各向异性蚀刻以提供从邻近第一导电壁的第一导电层向上延伸的第一电介质壁。 接着将第三导电层施加在第一导电和电介质壁上。 然后对其进行各向异性蚀刻以提供从邻近第一介电壁的第一导电层向上延伸的第二导电壁。 然后从晶片蚀刻第一电介质壁。 然后施加电容器介电层，随后是第四导电层以形成上电容器板。

公开(公告)号：US5049517A

公开(公告)日：1991-09-17

申请号：US612402

申请日：1990-11-07

申请人： Yauh-Ching Liu ,  Pierre Fazan ,  Hiang Chan ,  Howard E. Rhodes ,  Charles H. Dennison

发明人： Yauh-Ching Liu ,  Pierre Fazan ,  Hiang Chan ,  Howard E. Rhodes ,  Charles H. Dennison

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90

摘要： A method is disclosed for forming a capacitor on a semiconductor wafer which utilizes top and back sides of a capacitor node for capacitance maximization. First and second dielectric layers, having different etch rates, are applied atop the wafer, and a contact opening is etched therethrough. Poly is applied and etched to begin formation of one node of the capacitor. A layer of oxide is then formed atop the poly capacitor node. The first dielectric layer is then etched, leaving a projecting or floating capacitor node which is surrounded by the second dielectric material and oxide formed thereatop. The surrounding material is then etched, the capacitor dielectric applied, and the poly of the second capacitor nod applied and selectively etched.

摘要翻译： 公开了一种用于在半导体晶片上形成电容器的方法，其利用电容器节点的顶侧和背面进行电容最大化。 具有不同蚀刻速率的第一和第二电介质层被施加在晶片顶上，并且通过其蚀刻接触开口。 聚合物被施加和蚀刻以开始形成电容器的一个节点。 然后在聚电容器节点的顶部形成一层氧化物。 然后蚀刻第一介电层，留下由第二电介质材料和形成于其上的氧化物包围的突出或浮动电容器节点。 然后蚀刻周围的材料，施加电容器电介质，并施加第二电容器的点和点蚀。