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公开(公告)号：US5061650A
公开(公告)日：1991-10-29
申请号：US643835
申请日：1991-01-17
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L28/91 , H01L27/10817
摘要： A method is disclosed for forming a capacitor on a semiconductor wafer. A first electrically conductive layer is applied atop the wafer and engages exposed active areas. A first dielectric layer is next applied. The first dielectric and conductive layers are then patterned to define an outline for the lower capacitor plate. A second dielectric layer, having an etch rate which is slower than the first, is then applied and planarized or otherwise etched down to the first dielectric layer. The first dielectric layer is then etched down to the first conductive layer to produce upwardly projecting walls of second dielectric material surrounding the lower capacitor plate outline. A second electrically conductive layer is then applied. It is then anisotropically etched to provide a first electrically conductive wall extending upwardly from the first conductive layer. A third dielectric layer is then applied. The third dielectric layer is then anisotropicallly etched to provide a first dielectric wall extending upwardly from the first conductive layer adjacent the first conductive wall. A third electrically conductive layer is next applied over the first conductive and dielectric walls. It is then anisotropically etched to provide a second electrically conductive wall extending upwardly from the first conductive layer adjacent the first dielectric wall. The first dielectric wall is then etched from the wafer. A capacitor dielectric layer is then applied, followed by a fourth electrically conductive layer to form an upper capacitor plate.
摘要翻译： 公开了一种在半导体晶片上形成电容器的方法。 将第一导电层施加在晶片顶部并接合暴露的有源区。 接下来应用第一电介质层。 然后将第一介电层和导电层图案化以限定下电容器板的轮廓。 然后施加具有比第一介质层慢的蚀刻速率的第二介电层，并将其平坦化或以其它方式蚀刻到第一介电层。 然后将第一电介质层向下蚀刻到第一导电层，以产生围绕较低电容器板轮廓的第二介电材料的向上突出的壁。 然后施加第二导电层。 然后对其进行各向异性蚀刻以提供从第一导电层向上延伸的第一导电壁。 然后施加第三介电层。 然后对第三电介质层进行各向异性蚀刻以提供从邻近第一导电壁的第一导电层向上延伸的第一电介质壁。 接着将第三导电层施加在第一导电和电介质壁上。 然后对其进行各向异性蚀刻以提供从邻近第一介电壁的第一导电层向上延伸的第二导电壁。 然后从晶片蚀刻第一电介质壁。 然后施加电容器介电层，随后是第四导电层以形成上电容器板。
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公开(公告)号：US5049517A
公开(公告)日：1991-09-17
申请号：US612402
申请日：1990-11-07
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90
摘要： A method is disclosed for forming a capacitor on a semiconductor wafer which utilizes top and back sides of a capacitor node for capacitance maximization. First and second dielectric layers, having different etch rates, are applied atop the wafer, and a contact opening is etched therethrough. Poly is applied and etched to begin formation of one node of the capacitor. A layer of oxide is then formed atop the poly capacitor node. The first dielectric layer is then etched, leaving a projecting or floating capacitor node which is surrounded by the second dielectric material and oxide formed thereatop. The surrounding material is then etched, the capacitor dielectric applied, and the poly of the second capacitor nod applied and selectively etched.
摘要翻译： 公开了一种用于在半导体晶片上形成电容器的方法，其利用电容器节点的顶侧和背面进行电容最大化。 具有不同蚀刻速率的第一和第二电介质层被施加在晶片顶上，并且通过其蚀刻接触开口。 聚合物被施加和蚀刻以开始形成电容器的一个节点。 然后在聚电容器节点的顶部形成一层氧化物。 然后蚀刻第一介电层，留下由第二电介质材料和形成于其上的氧化物包围的突出或浮动电容器节点。 然后蚀刻周围的材料，施加电容器电介质，并施加第二电容器的点和点蚀。
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公开(公告)号：US5262343A
公开(公告)日：1993-11-16
申请号：US852822
申请日：1992-03-06
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/70
CPC分类号： H01L27/10852 , H01L28/40
摘要： This invention relates to semiconductor circuit memory storage devices and more particularly to a process to develop three-dimensional stacked capacitor cells using a high dielectric constant material as a storage cell dielectric and a combination of conductively doped polysilicon and metal silicide as the capacitor plates of a storage cell for use in high-density dynamic random access memory (DRAM) arrays. The present invention teaches how to fabricate three-dimensional stacked capacitors by modifying an existing stacked capacitor fabrication process to construct the three-dimensional stacked capacitor cell incorporating a high dielectric constant material as the cell dielectric that will allow denser storage cell fabrication with minimal increases of overall memory array dimensions. A capacitance gain of 3 to 10.times. or more over that of a conventional 3-dimensional storage cell is gained by using a high dielectric constant material as the storage cell dielectric.
摘要翻译： 本发明涉及半导体电路存储器存储器件，更具体地说，涉及使用高介电常数材料作为存储单元电介质和导电掺杂多晶硅和金属硅化物的组合来开发三维叠层电容器单元的方法，作为电容器板 用于高密度动态随机存取存储器（DRAM）阵列的存储单元。 本发明教导了如何通过修改现有的层叠电容器制造工艺来制造三维层叠电容器，以构建结合有高介电常数材料的三维叠层电容器单元作为电池电介质，其将使得更密集的存储单元制造以最小的增加 整体内存阵列尺寸。 通过使用高介电常数材料作为存储单元电介质，获得比常规3维存储单元的电容增益高3至10倍或更多的电容增益。
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公开(公告)号：US5053351A
公开(公告)日：1991-10-01
申请号：US671312
申请日：1991-03-19
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/87 , Y10S257/90
摘要： An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to hereinafter as a stacked E cell or SEC. The SEC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The SEC is made up of a polysilicon storage node structure having an E-shaped cross-sectional upper portion and a lower portion making contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed SEC capacitor. With the 3-dimensional shape and a texturized surface of a polysilicon storage node plate, substantial capacitor plate surface area of 3 to 5X is gained at the storage node.
摘要翻译： 修改现有的堆叠电容器制造工艺以构建三维叠层电容器，以下称为堆叠的E电池或SEC。 SEC设计定义了一种电容器存储单元，其在本发明中用于DRAM工艺。 SEC由具有E形横截面上部的多晶硅存储节点结构和通过埋入触点与有源区接触的下部组成。 多晶硅存储节点结构被多晶硅覆盖，其间夹有介质以形成完整的SEC电容器。 利用三维形状和多晶硅储存节点板的纹理化表面，在存储节点处获得3至5X的实质电容器板表面积。
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公开(公告)号：US5084406A
公开(公告)日：1992-01-28
申请号：US724026
申请日：1991-07-01
IPC分类号： G11C11/401 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/10 , H01L27/108
CPC分类号： H01L23/53271 , H01L21/768 , H01L23/5283 , H01L2924/0002
摘要： A DRAM fabrication process is disclosed for constructing a reduced resistance digit-line. The digit-line is so constructed as to maintain low resistance as it crosses the gaps between word-lines. By bridging gaps having a dimension less than or falling below a calculated critical gap spacing, and following the contours of gaps having a dimension greater or falling above that critical gap dimension, the digit-line resistance can be minimized.
摘要翻译： 公开了用于构造减小电阻数字线的DRAM制造工艺。 数字线被构造成当它跨越字线之间的间隙时保持低电阻。 通过桥接具有小于或低于计算的临界间隙的尺寸的间隙，并且跟随具有大于或低于该临界间隙尺寸的尺寸的间隙的轮廓，可以使数字线电阻最小化。
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公开(公告)号：US5234858A
公开(公告)日：1993-08-10
申请号：US614770
申请日：1990-11-16
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10817
摘要： A stacked surrounding wall capacitor (SSWC) using a modified stacked capacitor storage cell fabrication process. The SSWC is made up of polysilicon structure, having an elongated v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal buried digit line stacked capacitor cell.
摘要翻译： 堆叠围墙电容器（SSWC）采用改进的叠层电容器存储单元制造工艺。 SSWC由多晶硅结构组成，具有细长的V形横截面，位于掩埋接触处并延伸到覆盖有多个介质的介电层之间的多晶硅的相邻存储节点。 多晶硅结构的添加增加了存储能力50％，而不会扩大为正常埋地数字线叠层电容器电池定义的表面积。
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公开(公告)号：US5100825A
公开(公告)日：1992-03-31
申请号：US614892
申请日：1990-11-16
IPC分类号： H01L21/02
摘要： A stacked surrounding reintrant wall capacitor (SSRWC) using a modified stacked capacitor storage cell fabrication process. The SSRWC is made up of polysilicon structure, having an elongated v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal stacked capacitor cell.
摘要翻译： 使用改进的堆叠电容器存储单元制造工艺的堆叠围绕的重入壁电容器（SSRWC）。 SSRWC由多晶硅结构组成，具有细长的V形横截面，位于掩埋接触处并且延伸到由多晶硅覆盖的相邻存储节点，介电夹在其间。 多晶硅结构的添加增加了存储能力50％，而不会增加正常堆叠电容器单元所定义的表面积。
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公开(公告)号：US5234855A
公开(公告)日：1993-08-10
申请号：US633595
申请日：1990-12-21
申请人： Howard E. Rhodes , Hiang C. Chan , Charles H. Dennison , Yauh-Ching Liu , Pierre C. Fazan , Gurtej S. Sandhu
发明人： Howard E. Rhodes , Hiang C. Chan , Charles H. Dennison , Yauh-Ching Liu , Pierre C. Fazan , Gurtej S. Sandhu
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/87 , H01L28/91
摘要： A stacked comb spacer capacitor (SCSC) using a modified stacked capacitor storage cell fabrication process. The SCSC is made up of polysilicon structure, having a spiked v-shaped (or comb-shaped) cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The creation of the spiked polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal buried digit line stacked capacitor cell. Removing the dielectric residing under the backside of the storage node cell plate and filling that area with polysilicon increases storage capacity by an additional 50% or more.
摘要翻译： 使用改进的堆叠电容器存储单元制造工艺的堆叠梳状间隔电容器（SCSC）。 SCSC由多晶硅结构组成，具有加深的V形（或梳状）横截面，位于掩埋接触处，并延伸到由多晶硅覆盖的相邻存储节点和介于其间的电介质。 掺杂多晶硅结构的产生增加了存储能力50％，而不会扩大为正常埋地数字线叠层电容器单元定义的表面积。 去除位于存储节点单元板背面的电介质并用多晶硅填充该区域将存储容量提高了50％以上。
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9.发明授权Method for increasing capacitive surface area of a conductive material in semiconductor processing and stacked memory cell capacitor 失效用于增加半导体处理中的导电材料的电容表面积的方法和堆叠的存储单元电容器
公开(公告)号：US5170233A
公开(公告)日：1992-12-08
申请号：US722854
申请日：1991-06-27
IPC分类号： H01L21/02 , H01L27/108 , H01L29/92
CPC分类号： H01L27/10817 , H01L28/87 , H01L28/90
摘要： A method of fabricating a semiconductor wafer comprises providing an electrically conductive area on a semiconductor wafer. Multiple alternating layers of first and second materials are provided atop the wafer. The first and second materials need be selectively etchable relative to one another. The multiple layers are etched and the electrically conductive area upwardly exposed to define exposed edges of the multiple layers projecting upwardly from the electrically conductive area. One of the first or second materials is selectively isotropically etched relative to the other to produce indentations which extend generally laterally into the exposed edges of the multiple layers. A layer of electrically conductive material is applied atop the wafer and electrically conductive area, and fills the exposed edge indentations. The electrically conductive material is etched to leave conductive material extending upwardly from the electrically conductive area adjacent the multiple layer edges and within the indentations. The multiple layers are etched from the wafer to leave upwardly projecting conductive material having lateral projections extending therefrom. Such material is used to form the lower plate of a capacitor.
摘要翻译： 制造半导体晶片的方法包括在半导体晶片上提供导电区域。 将第一和第二材料的多个交替层设置在晶片顶部。 第一和第二材料需要相对于彼此可选择性地蚀刻。 蚀刻多个层，并且导电区域向上暴露以限定从导电区域向上突出的多个层的暴露边缘。 第一或第二材料之一相对于另一材料选择性地各向同性地蚀刻，以产生大致横向延伸到多层的暴露边缘的凹痕。 将一层导电材料施加在晶片和导电区域顶部，并填充暴露的边缘凹陷。 蚀刻导电材料以留下从邻近多层边缘和凹陷内的导电区域向上延伸的导电材料。 从晶片上蚀刻多层以留下向上突出的具有从其延伸的侧向突起的导电材料。 这种材料用于形成电容器的下板。
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公开(公告)号：US5084405A
公开(公告)日：1992-01-28
申请号：US712308
申请日：1991-06-07
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91 , H01L28/92
摘要： An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to as a Double Ring Stacked Cell or DRSC. The DRSC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The DRSC is made up of a polysilicon storage node structure having circular polysilicon ringed upper portion centered about a lower portion that makes contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed DRSC capacitor. The novel 3-dimensional shaped polysilicon storage node plate having double polysilicon rings, allows substantial capacitor plate surface area of 200% or more to be gained at the storage node over that of a conventional STC.
摘要翻译： 现有的叠层电容器制造工艺被修改以构建称为双环叠层电池或DRSC的三维堆叠电容器。 DRSC设计定义了在本发明中用于DRAM处理的电容器存储单元。 DRSC由多晶硅存储节点结构组成，其具有环形多晶硅环形上部，其中心部分以下部分为中心，其通过埋入触点与有源区接触。 多晶硅存储节点结构由多晶硅覆盖，其间夹有介质以形成完整的DRSC电容器。 具有双多晶硅环的新颖的三维多晶硅储存节点板允许在存储节点处获得大于常规STC的电容器板表面积为200％或更大的电容器板表面积。
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