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公开(公告)号：US5061650A
公开(公告)日：1991-10-29
申请号：US643835
申请日：1991-01-17
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L28/91 , H01L27/10817
摘要： A method is disclosed for forming a capacitor on a semiconductor wafer. A first electrically conductive layer is applied atop the wafer and engages exposed active areas. A first dielectric layer is next applied. The first dielectric and conductive layers are then patterned to define an outline for the lower capacitor plate. A second dielectric layer, having an etch rate which is slower than the first, is then applied and planarized or otherwise etched down to the first dielectric layer. The first dielectric layer is then etched down to the first conductive layer to produce upwardly projecting walls of second dielectric material surrounding the lower capacitor plate outline. A second electrically conductive layer is then applied. It is then anisotropically etched to provide a first electrically conductive wall extending upwardly from the first conductive layer. A third dielectric layer is then applied. The third dielectric layer is then anisotropicallly etched to provide a first dielectric wall extending upwardly from the first conductive layer adjacent the first conductive wall. A third electrically conductive layer is next applied over the first conductive and dielectric walls. It is then anisotropically etched to provide a second electrically conductive wall extending upwardly from the first conductive layer adjacent the first dielectric wall. The first dielectric wall is then etched from the wafer. A capacitor dielectric layer is then applied, followed by a fourth electrically conductive layer to form an upper capacitor plate.
摘要翻译： 公开了一种在半导体晶片上形成电容器的方法。 将第一导电层施加在晶片顶部并接合暴露的有源区。 接下来应用第一电介质层。 然后将第一介电层和导电层图案化以限定下电容器板的轮廓。 然后施加具有比第一介质层慢的蚀刻速率的第二介电层，并将其平坦化或以其它方式蚀刻到第一介电层。 然后将第一电介质层向下蚀刻到第一导电层，以产生围绕较低电容器板轮廓的第二介电材料的向上突出的壁。 然后施加第二导电层。 然后对其进行各向异性蚀刻以提供从第一导电层向上延伸的第一导电壁。 然后施加第三介电层。 然后对第三电介质层进行各向异性蚀刻以提供从邻近第一导电壁的第一导电层向上延伸的第一电介质壁。 接着将第三导电层施加在第一导电和电介质壁上。 然后对其进行各向异性蚀刻以提供从邻近第一介电壁的第一导电层向上延伸的第二导电壁。 然后从晶片蚀刻第一电介质壁。 然后施加电容器介电层，随后是第四导电层以形成上电容器板。
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公开(公告)号：US5049517A
公开(公告)日：1991-09-17
申请号：US612402
申请日：1990-11-07
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90
摘要： A method is disclosed for forming a capacitor on a semiconductor wafer which utilizes top and back sides of a capacitor node for capacitance maximization. First and second dielectric layers, having different etch rates, are applied atop the wafer, and a contact opening is etched therethrough. Poly is applied and etched to begin formation of one node of the capacitor. A layer of oxide is then formed atop the poly capacitor node. The first dielectric layer is then etched, leaving a projecting or floating capacitor node which is surrounded by the second dielectric material and oxide formed thereatop. The surrounding material is then etched, the capacitor dielectric applied, and the poly of the second capacitor nod applied and selectively etched.
摘要翻译： 公开了一种用于在半导体晶片上形成电容器的方法，其利用电容器节点的顶侧和背面进行电容最大化。 具有不同蚀刻速率的第一和第二电介质层被施加在晶片顶上，并且通过其蚀刻接触开口。 聚合物被施加和蚀刻以开始形成电容器的一个节点。 然后在聚电容器节点的顶部形成一层氧化物。 然后蚀刻第一介电层，留下由第二电介质材料和形成于其上的氧化物包围的突出或浮动电容器节点。 然后蚀刻周围的材料，施加电容器电介质，并施加第二电容器的点和点蚀。
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公开(公告)号：US5262343A
公开(公告)日：1993-11-16
申请号：US852822
申请日：1992-03-06
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/70
CPC分类号： H01L27/10852 , H01L28/40
摘要： This invention relates to semiconductor circuit memory storage devices and more particularly to a process to develop three-dimensional stacked capacitor cells using a high dielectric constant material as a storage cell dielectric and a combination of conductively doped polysilicon and metal silicide as the capacitor plates of a storage cell for use in high-density dynamic random access memory (DRAM) arrays. The present invention teaches how to fabricate three-dimensional stacked capacitors by modifying an existing stacked capacitor fabrication process to construct the three-dimensional stacked capacitor cell incorporating a high dielectric constant material as the cell dielectric that will allow denser storage cell fabrication with minimal increases of overall memory array dimensions. A capacitance gain of 3 to 10.times. or more over that of a conventional 3-dimensional storage cell is gained by using a high dielectric constant material as the storage cell dielectric.
摘要翻译： 本发明涉及半导体电路存储器存储器件，更具体地说，涉及使用高介电常数材料作为存储单元电介质和导电掺杂多晶硅和金属硅化物的组合来开发三维叠层电容器单元的方法，作为电容器板 用于高密度动态随机存取存储器（DRAM）阵列的存储单元。 本发明教导了如何通过修改现有的层叠电容器制造工艺来制造三维层叠电容器，以构建结合有高介电常数材料的三维叠层电容器单元作为电池电介质，其将使得更密集的存储单元制造以最小的增加 整体内存阵列尺寸。 通过使用高介电常数材料作为存储单元电介质，获得比常规3维存储单元的电容增益高3至10倍或更多的电容增益。
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公开(公告)号：US5053351A
公开(公告)日：1991-10-01
申请号：US671312
申请日：1991-03-19
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/87 , Y10S257/90
摘要： An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to hereinafter as a stacked E cell or SEC. The SEC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The SEC is made up of a polysilicon storage node structure having an E-shaped cross-sectional upper portion and a lower portion making contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed SEC capacitor. With the 3-dimensional shape and a texturized surface of a polysilicon storage node plate, substantial capacitor plate surface area of 3 to 5X is gained at the storage node.
摘要翻译： 修改现有的堆叠电容器制造工艺以构建三维叠层电容器，以下称为堆叠的E电池或SEC。 SEC设计定义了一种电容器存储单元，其在本发明中用于DRAM工艺。 SEC由具有E形横截面上部的多晶硅存储节点结构和通过埋入触点与有源区接触的下部组成。 多晶硅存储节点结构被多晶硅覆盖，其间夹有介质以形成完整的SEC电容器。 利用三维形状和多晶硅储存节点板的纹理化表面，在存储节点处获得3至5X的实质电容器板表面积。
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公开(公告)号：US5371701A
公开(公告)日：1994-12-06
申请号：US223477
申请日：1994-04-05
IPC分类号： H01L27/108 , H01L29/68
CPC分类号： H01L27/10817
摘要： A stacked delta cell (SDC) capacitor using a modified stacked capacitor storage cell fabrication process. The SDC is made up of polysilicon structure, having an inverted deltoid cross section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 120% without enlarging the surface area defined for a normal stacked capacitor cell.
摘要翻译： 使用改进的堆叠电容器存储单元制造工艺的堆叠三角形电池（SDC）电容器。 SDC由具有倒三角形横截面的多晶硅结构构成，位于掩埋接触处，并延伸到由多晶硅覆盖的相邻存储节点之间，介电夹在其间。 多晶硅结构的添加增加了存储能力120％，而不会扩大为正常层叠电容器单元限定的表面积。
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公开(公告)号：US5084405A
公开(公告)日：1992-01-28
申请号：US712308
申请日：1991-06-07
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91 , H01L28/92
摘要： An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to as a Double Ring Stacked Cell or DRSC. The DRSC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The DRSC is made up of a polysilicon storage node structure having circular polysilicon ringed upper portion centered about a lower portion that makes contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed DRSC capacitor. The novel 3-dimensional shaped polysilicon storage node plate having double polysilicon rings, allows substantial capacitor plate surface area of 200% or more to be gained at the storage node over that of a conventional STC.
摘要翻译： 现有的叠层电容器制造工艺被修改以构建称为双环叠层电池或DRSC的三维堆叠电容器。 DRSC设计定义了在本发明中用于DRAM处理的电容器存储单元。 DRSC由多晶硅存储节点结构组成，其具有环形多晶硅环形上部，其中心部分以下部分为中心，其通过埋入触点与有源区接触。 多晶硅存储节点结构由多晶硅覆盖，其间夹有介质以形成完整的DRSC电容器。 具有双多晶硅环的新颖的三维多晶硅储存节点板允许在存储节点处获得大于常规STC的电容器板表面积为200％或更大的电容器板表面积。
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公开(公告)号：US5219778A
公开(公告)日：1993-06-15
申请号：US800803
申请日：1991-11-27
申请人： Charles H. Dennison , Ruojia Lee , Yauh-Ching Liu , Pierre Fazan
发明人： Charles H. Dennison , Ruojia Lee , Yauh-Ching Liu , Pierre Fazan
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/40
摘要： A stacked v-cell (SVC) capacitor using a modified stacked capacitor storage cell fabrication process. The SVC capacitor is made up of polysilicon structure, having a v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 70% without enlarging the surface area defined for a normal stacked capacitor cell.
摘要翻译： 使用改进的堆叠电容器存储单元制造工艺的堆叠的v电池（SVC）电容器。 SVC电容器由具有V形横截面的多晶硅结构组成，位于掩埋接触处并且延伸到由多晶硅覆盖的相邻存储节点之间，介电夹在其间。 多晶硅结构的添加增加了存储能力70％，而不会扩大为正常层叠电容器单元所定义的表面积。
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公开(公告)号：US5321649A
公开(公告)日：1994-06-14
申请号：US76300
申请日：1993-06-11
IPC分类号： H01L27/108 , H01L29/68
CPC分类号： H01L27/10817
摘要： A stacked delta cell (SDC) capacitor using a modified stacked capacitor storage cell fabrication process. The SDC is made up of polysilicon structure, having an inverted deltoid cross section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 120% without enlarging the surface area defined for a normal stacked capacitor cell.
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公开(公告)号：US5236860A
公开(公告)日：1993-08-17
申请号：US799461
申请日：1991-11-26
申请人： Pierre Fazan , Gurtej S. Sandhu , Hiang C. Chan , Yauh-Ching Liu
发明人： Pierre Fazan , Gurtej S. Sandhu , Hiang C. Chan , Yauh-Ching Liu
IPC分类号： H01L27/108
CPC分类号： H01L27/10817
摘要： A lateral extension stacked capacitor (LESC) using a modified stacked capacitor storage cell fabrication process. The LESC is made up of polysilicon structure, having a spherical ended v-shaped cross-section. The storage node plate of the LESC is overlaid by polysilicon with a dielectric sandwiched in between and connects to an access device's active area via a buried contact. The plate extends to an adjacent storage node but is isolated from the adjacent node by less than the critical resolution dimension of a given lithographic technology. The addition of the polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal buried digit line stacked capacitor cell.
摘要翻译： 一种侧向延伸堆叠电容器（LESC），采用改进的堆叠电容器存储单元制造工艺。 LESC由多晶硅结构组成，具有球形末端的V形横截面。 LESC的存储节点板由介质夹在其间的多晶硅覆盖，并通过埋入触点连接到接入设备的有源区。 板延伸到相邻的存储节点，但是通过小于给定光刻技术的临界分辨率尺寸与相邻节点隔离。 多晶硅结构的添加增加了存储能力50％，而不会扩大为正常埋地数字线叠层电容器电池定义的表面积。
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公开(公告)号：US5082797A
公开(公告)日：1992-01-21
申请号：US645086
申请日：1991-01-22
申请人： Hiang C. Chan , Pierre Fazan , Yauh-Ching Liu
发明人： Hiang C. Chan , Pierre Fazan , Yauh-Ching Liu
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/90
摘要： A stacked textured container capacitor (STCC) using a modified stacked capacitor storage cell fabrication process. The STCC is made up of a texturized polysilicon structure, having an elongated u-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. With the 3-dimensional shape and texturized surface of a polysilicon storage node plate substantial capacitor plate surface area of 200% or more is gained at the storage node.
摘要翻译： 使用改进的堆叠电容器存储单元制造工艺的堆叠纹理容器电容器（STCC）。 STCC由纹理化的多晶硅结构组成，具有细长的u形横截面，位于掩埋的接触处并且延伸到由多晶硅覆盖的相邻存储节点，介电夹在其间。 在多晶硅储存节点板的3维形状和纹理化表面上，在存储节点处获得基本上电容器板表面积为200％以上的表面积。
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