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公开(公告)号：US5442642A
公开(公告)日：1995-08-15
申请号：US989403
申请日：1992-12-11
IPC分类号： G01R31/3185 , G06F11/267 , G06F11/27 , G11C29/14 , H04B17/00
CPC分类号： G01R31/318505 , G06F11/267 , G06F11/27 , G11C29/14
摘要： A test system is added to a substrate and a test mode of operation is added to the timing and control functions of a system on the substrate. When a multifunctional system on the substrate is tested, a first functional subsystem is connected to an external tester. The tester causes the timing and control system to enter the test mode of operation. When in the test mode of operation, the test system provides a signal derived from a signal generator on the substrate. The generated signal is coupled to a second functional subsystem so that functional independence of the first and second subsystems can be verified.
摘要翻译： 将测试系统添加到衬底中，并且将测试操作模式添加到衬底上的系统的定时和控制功能。 当测试基板上的多功能系统时，第一功能子系统连接到外部测试器。 测试仪使定时和控制系统进入测试操作模式。 当处于测试操作模式时，测试系统提供从基板上的信号发生器得到的信号。 所生成的信号耦合到第二功能子系统，使得能够验证第一和第二子系统的功能独立性。
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2.发明授权System having multiple subsystems and test signal source resident upon common substrate 失效具有多个子系统和测试信号源的系统驻留在公共基板上
公开(公告)号：US5499250A
公开(公告)日：1996-03-12
申请号：US443818
申请日：1995-05-18
IPC分类号： G01R31/3185 , G06F11/267 , G06F11/27 , G11C29/14 , H04B1/16
CPC分类号： G01R31/318505 , G06F11/267 , G06F11/27 , G11C29/14
摘要： A system has multiple subsystems and a test signal source resident upon a common substrate. A first subsystem interfaces with an off-substrate functional tester during a test. The test signal source generates a first signal during the test for input to the second subsystem. The second subsystem responds performing an operation independent of operation and current state of the first subsystem. The functional tester verifies the independent operation of the first and second subsystems.
摘要翻译： 系统具有驻留在公共基板上的多个子系统和测试信号源。 在测试期间，第一子系统与离基板功能测试仪接口。 测试信号源在测试期间产生第一信号以输入到第二子系统。 第二子系统响应执行独立于第一子系统的操作和当前状态的操作。 功能测试器验证第一和第二子系统的独立操作。
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3.发明授权System having multiple subsystems and test signal source resident upon common substrate 失效具有多个子系统和测试信号源的系统驻留在公共基板上
公开(公告)号：US5648974A
公开(公告)日：1997-07-15
申请号：US572117
申请日：1995-12-14
IPC分类号： G01R31/3185 , G06F11/267 , G06F11/27 , G11C29/14 , H04B15/00
CPC分类号： G01R31/318505 , G06F11/267 , G06F11/27 , G11C29/14
摘要： A system has multiple subsystems and a test signal source resident upon a common substrate. A first subsystem interfaces with an off-substrate functional tester during a test. The test signal source generates a first signal during the test for input to the second subsystem. The second subsystem responds performing an operation independent of operation and current state of the first subsystem. The functional tester verifies the independent operation of the first and second subsystems.
摘要翻译： 系统具有驻留在公共基板上的多个子系统和测试信号源。 在测试期间，第一子系统与离基板功能测试仪接口。 测试信号源在测试期间产生第一信号以输入到第二子系统。 第二子系统响应执行独立于第一子系统的操作和当前状态的操作。 功能测试器验证第一和第二子系统的独立操作。
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公开(公告)号：US06809974B2
公开(公告)日：2004-10-26
申请号：US10231513
申请日：2002-08-29
IPC分类号： G11C700
摘要： A method of monitoring the characteristics of a delay locked loop (DLL) in a memory device during a test mode is provided. The DLL generates an internal clock signal based on an external clock signal. The external and internal clock signals are normally synchronized. DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during a test mode.
摘要翻译： 提供了一种在测试模式期间监视存储器件中的延迟锁定环（DLL）的特性的方法。 DLL根据外部时钟信号产生内部时钟信号。 外部和内部时钟信号通常是同步的。 DLL不断响应存储器件的工作状态的变化，以保持外部和内部时钟同步。 该方法涉及防止DLL响应于在测试模式期间存储器件的电源电压变化的操作条件的改变。
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公开(公告)号：US5945845A
公开(公告)日：1999-08-31
申请号：US112905
申请日：1998-07-09
申请人： Mark R. Thomann , Paul M. Fuller
发明人： Mark R. Thomann , Paul M. Fuller
IPC分类号： H03K19/017 , H03K19/01 , H03K19/094
CPC分类号： H03K19/01721
摘要： A voltage elevation circuit supplying additional voltage for gate switching having an elevated power supply connected to a first node of a capacitor using a transistor. The elevated power supply and booting circuit providing additional voltage for gate switching applications. One application is a MOSFET output driver application having a 3 Volt power supply. One configuration using a switch to charge a capacitor using a first voltage supply and then providing additional voltage by a boot device and by switching in an elevated power supply to maintain an elevated voltage at the node.
摘要翻译： 提供用于栅极切换的附加电压的电压升高电路，其具有使用晶体管连接到电容器的第一节点的升高的电源。 升压的电源和引导电路为栅极开关应用提供额外的电压。 一个应用是具有3伏特电源的MOSFET输出驱动器应用。 一种配置，其使用开关来使用第一电压源对电容器充电，然后通过引导装置提供额外的电压，并且通过切换升高的电源来维持节点处的升高的电压。
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公开(公告)号：US5574390A
公开(公告)日：1996-11-12
申请号：US493912
申请日：1995-06-23
申请人： Mark R. Thomann
发明人： Mark R. Thomann
IPC分类号： H03K19/017 , H03K19/0175 , H03K19/082
CPC分类号： H03K19/01721
摘要： A voltage elevation circuit supplying additional voltage for gate switching having an elevated power supply connected to a first node of a capacitor using a transistor. The elevated power supply and booting circuit providing additional voltage for gate switching applications. One application is a MOSFET output driver application having a 3 Volt power supply where noise margin demands elevated switching voltages. One configuration using a long channel transistor to limit current sourced by the elevated power supply. An alternate configuration using a switched elevated power supply to minimize loading on the elevated power supply.
摘要翻译： 提供用于栅极切换的附加电压的电压升高电路，其具有使用晶体管连接到电容器的第一节点的升高的电源。 升压的电源和引导电路为栅极开关应用提供额外的电压。 一种应用是具有3伏电源的MOSFET输出驱动器应用，其中噪声余量要求提高开关电压。 一种使用长沟道晶体管来限制由高电源供电的电流的配置。 使用交换式高架电源的一种替代配置，以最大限度地减少高架电源的负载。
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7.发明授权Video random access memory device and method implementing independent two WE nibble control 失效视频随机存取存储器件和方法实现独立的两个WE半字节控制
公开(公告)号：US5506814A
公开(公告)日：1996-04-09
申请号：US69967
申请日：1993-05-28
申请人： Glen Hush , Mike Seibert , Jeff Mailloux , Mark R. Thomann
发明人： Glen Hush , Mike Seibert , Jeff Mailloux , Mark R. Thomann
CPC分类号： G11C7/1006 , G11C7/1033 , G11C7/1075
摘要： The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the method of the invention a first bank may be written independently of a second bank, such that during a single memory cycle the first bank may be written and the second bank may be read. The VRAM of the invention functions without the masking of a write to either bank. In addition the write memory function can be performed either through the random access memory port or through the serial access memory port.
摘要翻译： 本发明是具有多于一个写入控制引脚的单片视频随机存取存储器（VRAM）芯片，其用于将VRAM分割成具有四个DQ平面的存储体或子芯片，使得可以将数据的半字节写入VRAM 。 使用本发明的方法，可以独立于第二组来写入第一存储体，使得在单个存储器周期期间可以写入第一存储体并且可以读取第二存储体。 本发明的VRAM在不掩蔽任何一个存储体的写入的情况下起作用。 此外，写入存储器功能可以通过随机存取存储器端口或通过串行存取存储器端口执行。
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8.发明授权
公开(公告)号：US5469393A
公开(公告)日：1995-11-21
申请号：US122732
申请日：1993-09-15
申请人： Mark R. Thomann
发明人： Mark R. Thomann
CPC分类号： G11C29/04 , G11C29/50 , G11C11/401
摘要： The invention is a monolithic memory device having a circuit and a method for decreasing the cell margin during a test mode. Decreasing the cell margin stresses the memory device during the test mode greater than a stress experienced during normal operation, thus test time can be decreased.
摘要翻译： 本发明是具有在测试模式期间减小单元余量的电路和方法的单片存储器件。 在测试模式期间，减小电池余量会使存储器件大于在正常工作期间发生的应力，从而可以降低测试时间。
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公开(公告)号：US6081528A
公开(公告)日：2000-06-27
申请号：US806827
申请日：1997-02-26
申请人： Mark R. Thomann
发明人： Mark R. Thomann
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/405 , H04L2012/5627 , H04L2012/5652 , H04L2012/5681
摘要： An ATM switch including a multi-port memory is described. The multi-port memory having a dynamic random access memory (DRAM) and a plurality of input and output serial access memories (SAMs). Efficient, flexible transfer circuits and methods are described for transferring ATM data between the SAMs and the DRAM. The transfer circuits and methods include helper flip/flops to latch ATM data for editing prior to storage in the DRAM. Editing of ATM data transferred from the DRAM is also described. Dynamic parity generation and checking is described to detect errors induced during switching.
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公开(公告)号：US5657289A
公开(公告)日：1997-08-12
申请号：US511778
申请日：1995-08-30
申请人： Glen E. Hush , Mark R. Thomann
发明人： Glen E. Hush , Mark R. Thomann
IPC分类号： G11C11/401 , G11C7/10 , H04L12/56 , H04Q11/04 , G11C8/00
CPC分类号： H04L12/5601 , G11C7/1075 , H04L49/108 , H04Q11/0478 , H04L2012/5681
摘要： A multiport memory is described which includes a random access memory (RAM) and serial access memories (SAMs). The multiport memory is well suited for storing asynchronous transfer mode (ATM) data cells. Control circuitry is provided to allow the multiport memory to be easily configured for operating at different input data rates. This is accomplished by configuring several of the SAMs to store a portion of an input ATM cell on an input clock cycle. The full ATM cell is stored in less clock cycles and can be transferred from the SAMs to the RAM in a single transfer cycle.
摘要翻译： 描述了包括随机存取存储器（RAM）和串行存取存储器（SAM））的多端口存储器。 多端口存储器非常适用于存储异步传输模式（ATM）数据单元。 提供控制电路以允许容易地配置多端口存储器，以便以不同的输入数据速率进行操作。 这通过配置几个SAM来在输入时钟周期上存储输入ATM信元的一部分来实现。 完整的ATM信元以更少的时钟周期存储，并且可以在单个传输周期内从SAM传输到RAM。
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