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公开(公告)号：US07650549B2
公开(公告)日：2010-01-19
申请号：US11174193
申请日：2005-07-01
IPC分类号： G01R31/317 , G01R31/40
CPC分类号： G01R31/318552
摘要： A master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode multiplexer. Separate, non-overlapping clocking permits the elimination of hold violations in scan mode for scan mode flip flop chains, permitting the elimination of delay buffers in the scan mode data paths. Resulting application circuits have reduced circuit area, power consumption and noise generation. A clock generator for scan mode clocking is provided to obtain the separate, non-overlapping scan mode clocks. Scan mode clocks may be generated with a toggle flip flop, a pulse generator or a clock gating circuit.
摘要翻译： 在扫描模式期间，触发器的主器件和从器件级分别以不重叠的时钟信号时钟，以消除数据输入扫描模式多路复用器。 单独的，不重叠的时钟允许在扫描模式触发器链的扫描模式中消除保持违规，允许消除扫描模式数据路径中的延迟缓冲器。 所得到的应用电路减少了电路面积，功耗和噪声产生。 提供用于扫描模式时钟的时钟发生器以获得单独的非重叠扫描模式时钟。 扫描模式时钟可以用切换触发器，脉冲发生器或时钟门控电路产生。
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公开(公告)号：US07908535B2
公开(公告)日：2011-03-15
申请号：US12495046
申请日：2009-06-30
CPC分类号： G01R31/318536 , G01R31/318552 , G01R31/318558 , G01R31/318572
摘要： Memory compiler engineers often focus on the efficient implementation of the largest possible memory configurations for each memory type. The overhead of test and control circuitry within memory implementations is usually amortized across a large number of storage bits. Unfortunately, test structures generally do not scale down with decreasing memory sizes, creating a large area penalty for a design with numerous small memories. One solution is a scannable register file (SRF) architecture using scannable latch bit-cells laid out using a standard cell layout/power template. All sub-cells can be placed in standard cell rows and utilize standard cell power straps. Non-SRF standard cells can be abutted on all sides, placement keep-out regions are not needed. Metal utilization is usually limited to first three metallization layers. The bit-cell is much larger than standard compiled memory bit cells, but has no overhead beyond address decode, word-line drivers, and read-write data latches.
摘要翻译： 内存编译工程师经常专注于为每种内存类型高效地实现最大可能的内存配置。 存储器实现中的测试和控制电路的开销通常在大量存储位中分摊。 不幸的是，测试结构通常不会随着存储器尺寸的减小而缩小，对于具有许多小存储器的设计造成了大的面积损失。 一种解决方案是使用标准单元布局/电源模板布局的可扫描锁存位单元的可扫描寄存器文件（SRF）架构。 所有子单元可以放置在标准单元行中，并使用标准单元电源带。 非SRF标准电池可以在所有方面贴合，不需要放置保持区域。 金属利用通常限于前三个金属化层。 比特单元比标准编译的存储器位单元大得多，但是除了地址解码，字线驱动器和读写数据锁存器之外，没有开销。
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3.发明授权Digital storage element architecture comprising dual scan clocks and gated scan output 有权数字存储元件架构包括双扫描时钟和门控扫描输出公开(公告)号：US07596732B2
公开(公告)日：2009-09-29
申请号：US11171537
申请日：2005-06-30
IPC分类号： G01R31/28
CPC分类号： G01R31/318544
摘要： A digital storage element (e.g., a flip-flop or a latch) includes a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch includes dedicated functional data and scan data output ports. The digital storage element operates in a functional mode and in a scan mode. While in the scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch. The first and second clock signals are non-overlapping and, as such, avoid the digital storage element from creating hold violations.
摘要翻译： 数字存储元件（例如，触发器或锁存器）包括主透明锁存器，其从数据输入端口接收功能数据，并从耦合到主透明锁存器的扫描输入端口和从属透明锁存器扫描数据。 从机透明锁存器包括专用功能数据和扫描数据输出端口。 数字存储元件以功能模式和扫描模式工作。 在扫描模式下，从属透明锁存器使用第一个时钟信号，主器件透明锁存器使用第二个时钟信号。 第一和第二时钟信号是不重叠的，因此避免数字存储元件造成持续违规。
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4.发明授权Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch coupling based on control register content 有权通过基于控制寄存器内容的开关耦合，通过FFT和滤波器单元在协处理器和系统总线从器件到存储器块的流水线访问公开(公告)号：US07587577B2
公开(公告)日：2009-09-08
申请号：US11557755
申请日：2006-11-08
申请人： Marc E. Royer , Bharath M. Siravara , Steven C. Bartling , Charles M. Branch , Pedro R. Galabert , Neeraj Mogotra , Samil D. Kamath
发明人： Marc E. Royer , Bharath M. Siravara , Steven C. Bartling , Charles M. Branch , Pedro R. Galabert , Neeraj Mogotra , Samil D. Kamath
IPC分类号： G06F13/00
CPC分类号： G06F15/7864 , G06F9/3879 , Y02D10/13
摘要： A system architecture including a co-processor and a memory switch resource is disclosed. The memory switch includes multiple memory blocks and switch circuitry for selectably coupling processing units of the co-processor, and also a bus slave circuit coupled to a system bus of the system, to selected ones of the memory blocks. The memory switch may be constructed as an array of multiplexers, controlled by control logic of the memory switch in response to the contents of a control register. The various processing units of the co-processor are each able to directly access one of the memory blocks, as controlled by the switch circuitry. Following processing of a block of data by one of the processing units, the memory switch associates the memory blocks with other functional units, thus moving data from one functional unit to another without requiring reading and rewriting of the data.
摘要翻译： 公开了一种包括协处理器和存储器交换机资源的系统架构。 存储器开关包括多个存储器块和用于可选择地将协处理器的处理单元耦合的开关电路，以及耦合到系统的系统总线的总线从属电路到选择的存储器块。 存储器开关可以被构造为多路复用器的阵列，其由存储器开关的控制逻辑控制，以响应于控制寄存器的内容。 协处理器的各种处理单元各自能够直接访问由开关电路控制的存储块之一。 在由处理单元之一处理数据块之后，存储器开关将存储器块与其他功能单元相关联，从而将数据从一个功能单元移动到另一个功能单元，而不需要读取和重写数据。
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5.发明授权Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality 有权数字存储元件架构包括集成的2对1复用器功能公开(公告)号：US08692592B2
公开(公告)日：2014-04-08
申请号：US11172534
申请日：2005-06-30
IPC分类号： H03K21/00
CPC分类号： G11C29/48 , G11C29/32 , G11C2029/3202
摘要： A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port. The data input ports are coupled to a two-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.
摘要翻译： 数字存储元件包括从数据输入端口接收功能数据信号并从扫描输入端口扫描数据信号的主透明锁存器。 数据输入端口耦合到双输入单输出多路复用器，其适于接收功能数据信号并选择性地输出功能数据信号之一。 数字存储元件还包括耦合到主透明锁存器的从透明锁存器，从属透明锁存器包括专用功能数据和扫描数据输出端口。 当在扫描模式下操作时，从属透明锁存器使用第一时钟信号，并且主透明锁存器使用第二时钟信号，其中第一和第二时钟信号是不重叠的。
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公开(公告)号：US20100332929A1
公开(公告)日：2010-12-30
申请号：US12495046
申请日：2009-06-30
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318536 , G01R31/318552 , G01R31/318558 , G01R31/318572
摘要： Memory compiler engineers often focus on the efficient implementation of the largest possible memory configurations for each memory type. The overhead of test and control circuitry within memory implementations is usually amortized across a large number of storage bits. Unfortunately, test structures generally do not scale down with decreasing memory sizes, creating a large area penalty for a design with numerous small memories. One solution is a scannable register file (SRF) architecture using scannable latch bit-cells laid out using a standard cell layout/power template. All sub-cells can be placed in standard cell rows and utilize standard cell power straps. Non-SRF standard cells can be abutted on all sides, placement keep-out regions are not needed. Metal utilization is usually limited to first three metallization layers. The bit-cell is much larger than standard compiled memory bit cells, but has no overhead beyond address decode, word-line drivers, and read-write data latches.
摘要翻译： 内存编译工程师经常专注于为每种内存类型高效地实现最大可能的内存配置。 存储器实现中的测试和控制电路的开销通常在大量存储位中分摊。 不幸的是，测试结构通常不会随着存储器尺寸的减小而缩小，对于具有许多小存储器的设计造成了大的面积损失。 一种解决方案是使用标准单元布局/电源模板布局的可扫描锁存位单元的可扫描寄存器文件（SRF）架构。 所有子单元可以放置在标准单元行中，并使用标准单元电源带。 非SRF标准电池可以在所有方面贴合，不需要放置保持区域。 金属利用通常限于前三个金属化层。 比特单元比标准编译的存储器位单元大得多，但是除了地址解码，字线驱动器和读写数据锁存器之外，没有开销。
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7.发明授权Digital storage element architecture comprising integrated multiplexer and reset functionality 有权包括集成多路复用器和复位功能的数字存储元件架构公开(公告)号：US07274234B2
公开(公告)日：2007-09-25
申请号：US11171540
申请日：2005-06-30
IPC分类号： H03K3/289
CPC分类号： H03K3/0372 , G01R31/318575 , G01R31/318594 , G06F9/30141 , G06F9/3867 , G11C29/32 , G11C2029/3202
摘要： A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer that receives the functional data signals and selectively outputs one of the functional data signals. The element comprises a slave transparent latch coupled to the master transparent latch and comprising dedicated functional and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping. A first transistor is coupled to the master transparent latch and a second transistor is coupled to the slave transparent latch. When activated, the first or second transistor resets the element.
摘要翻译： 数字存储元件包括主透明锁存器，其从数据输入端口接收功能数据信号并从扫描输入端口扫描数据信号，数据输入端口耦合到四输入单输出多路复用器，其接收功能数据信号， 选择性地输出功能数据信号之一。 该元件包括耦合到主透明锁存器并且包括专用功能和扫描数据输出端口的从透明锁存器。 当在扫描模式下操作时，从属透明锁存器使用第一时钟信号，并且主透明锁存器使用第二时钟信号，其中第一和第二时钟信号是不重叠的。 第一晶体管耦合到主透明锁存器，第二晶体管耦合到从透明锁存器。 当被激活时，第一或第二晶体管复位元件。
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公开(公告)号：US07487417B2
公开(公告)日：2009-02-03
申请号：US11171528
申请日：2005-06-30
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318575 , G01R31/318594
摘要： A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. A clock gating element is also included that gates off a clock to the slave latch, and not the master transparent latch, based on an enable signal that is asserted to disable use of the digital storage element.
摘要翻译： 数字存储元件（例如，触发器或锁存器）包括主透明锁存器，其从数据输入端口接收功能数据，并从耦合到主透明锁存器的扫描输入端口和从属透明锁存器扫描数据。 从机透明锁存器包括专用功能数据和扫描数据输出端口。 还包括时钟门控元件，其基于被断言以禁用数字存储元件的使用的使能信号，将时钟关闭到从锁存器，而不是主器件透明锁存器。
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公开(公告)号：US20080259681A1
公开(公告)日：2008-10-23
申请号：US11736400
申请日：2007-04-17
IPC分类号： G11C11/40
CPC分类号： G11C11/412
摘要： Various systems and methods for implementing memory devices are disclosed. For example, some embodiments of the present invention provide sub-threshold memory devices that include a differential bit cell. Such a differential bit cell includes two PMOS transistors, two NMOS transistors, and two inverters. The source of the first PMOS transistor and the source of the second PMOS transistor are electrically coupled to a bit line input, and the source of the first NMOS transistor and the source of the second NMOS transistor are electrically coupled to the bit line input. The gate of the first NMOS transistor and the gate of the second NMOS transistor are electrically coupled to a word line input. The gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically coupled to an inverted version of the word line input. The drain of the first PMOS transistor is electrically coupled to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is electrically coupled to the drain of the second NMOS transistor. In addition, the drain of the first PMOS transistor is electrically coupled to the drain of the second PMOS transistor by the first inverter, and the drain of the second PMOS transistor is electrically coupled to the drain of the first PMOS transistor by the second inverter.
摘要翻译： 公开了用于实现存储器件的各种系统和方法。 例如，本发明的一些实施例提供了包括差分位单元的子阈值存储器件。 这种差分位单元包括两个PMOS晶体管，两个NMOS晶体管和两个反相器。 第一PMOS晶体管的源极和第二PMOS晶体管的源极电耦合到位线输入，并且第一NMOS晶体管的源极和第二NMOS晶体管的源极电耦合到位线输入。 第一NMOS晶体管的栅极和第二NMOS晶体管的栅极电耦合到字线输入。 第一PMOS晶体管的栅极和第二PMOS晶体管的栅极电耦合到字线输入的反相版本。 第一PMOS晶体管的漏极电耦合到第一NMOS晶体管的漏极，并且第二PMOS晶体管的漏极电耦合到第二NMOS晶体管的漏极。 此外，第一PMOS晶体管的漏极由第一反相器电耦合到第二PMOS晶体管的漏极，并且第二PMOS晶体管的漏极由第二反相器电耦合到第一PMOS晶体管的漏极。
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公开(公告)号：US20080258790A1
公开(公告)日：2008-10-23
申请号：US11736419
申请日：2007-04-17
IPC分类号： H03K3/0233
CPC分类号： H03K3/012 , H03K3/356139
摘要： Various systems and methods for capturing data are disclosed. For example, some embodiments of the present invention provide differential jam latches. Such differential jam latches include a data input, a latch input, and an output. Further, such differential jam latches include a PMOS stage and an NMOS stage. The PMOS stage includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor. The gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically coupled to an inverted version of the latch input. The gate of the third PMOS transistor is electrically coupled to the data input, and the gate of the fourth PMOS transistor is electrically coupled to an inverted version of the data input. The NMOS stage includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor. The gate of the first NMOS transistor and the gate of the second NMOS transistor are electrically coupled to the latch input. The gate of the third NMOS transistor is electrically coupled to the data input, and the gate of the fourth NMOS transistor is electrically coupled to an inverted version of the data input. In addition, the jam latches include two inverters. The PMOS stage is electrically coupled to a first node and a second node, and the NMOS stage is electrically coupled to the first node and the second node. The first inverter drives an inverted version of the signal on the first node to the second node, and the second inverter drives an inverted version of the signal on the second node to the first node.
摘要翻译： 公开了用于捕获数据的各种系统和方法。 例如，本发明的一些实施例提供差分卡锁闩锁。 这种差分阻塞锁存器包括数据输入，锁存器输入和输出。 此外，这种差分阻塞锁存器包括PMOS级和NMOS级。 PMOS级包括第一PMOS晶体管，第二PMOS晶体管，第三PMOS晶体管和第四PMOS晶体管。 第一PMOS晶体管的栅极和第二PMOS晶体管的栅极电耦合到锁存器输入的反相形式。 第三PMOS晶体管的栅极电耦合到数据输入，并且第四PMOS晶体管的栅极电耦合到数据输入的反相版本。 NMOS级包括第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 第一NMOS晶体管的栅极和第二NMOS晶体管的栅极电耦合到锁存器输入。 第三NMOS晶体管的栅极电耦合到数据输入，并且第四NMOS晶体管的栅极电耦合到数据输入的反相版本。 此外，卡锁闩锁包括两个逆变器。 PMOS级电耦合到第一节点和第二节点，并且NMOS级电耦合到第一节点和第二节点。 第一逆变器将第一节点上的信号的反相版本驱动到第二节点，并且第二反相器将第二节点上的信号的反转版本驱动到第一节点。
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