公开(公告)号：US20070284644A1

公开(公告)日：2007-12-13

申请号：US11423842

申请日：2006-06-13

申请人： Chen-Chin Liu ,  Chun-Pei Wu ,  Ta-Kang Chu ,  Yao-Fu Chan

发明人： Chen-Chin Liu ,  Chun-Pei Wu ,  Ta-Kang Chu ,  Yao-Fu Chan

IPC分类号： H01L29/76

CPC分类号： H01L29/4234 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/42324

摘要： A method for fabricating a floating gate memory device comprises using thin buried diffusion regions with increased encroachment by a buried diffusion oxide layer into the buried diffusion layer and underneath the tunnel oxide under the floating gate. Further, the floating gate polysilicon layer has a eight than the buried diffusion height. The increased step height of the gate polysilicon layer to the buried diffusion layer, and the increased encroachment of the buried diffusion oxide, can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

摘要翻译： 一种用于制造浮动栅极存储器件的方法，包括使用较薄的掩埋扩散区，其中埋入扩散氧化物层的埋入扩大到掩埋扩散层内并在浮动栅极下方的隧道氧化物下面。 此外，浮栅多晶硅层的掩埋扩散高度为8。 栅极多晶硅层对掩埋扩散层的阶梯高度增加以及掩埋扩散氧化物的侵蚀增加，可以产生较高的GCR，同时仍然允许使用虚拟接地阵列设计减小电池尺寸。

公开(公告)号：US08017480B2

公开(公告)日：2011-09-13

申请号：US11423842

申请日：2006-06-13

申请人： Chen-Chin Liu ,  Chun-Pei Wu ,  Ta-Kang Chu ,  Yao-Fu Chan

发明人： Chen-Chin Liu ,  Chun-Pei Wu ,  Ta-Kang Chu ,  Yao-Fu Chan

IPC分类号： H01L21/8234

CPC分类号： H01L29/4234 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/42324

摘要： A method for fabricating a floating gate memory device comprises using thin buried diffusion regions with increased encroachment by a buried diffusion oxide layer into the buried diffusion layer and underneath the tunnel oxide under the floating gate. Further, the floating gate polysilicon layer has a larger height than the buried diffusion height. The increased step height of the gate polysilicon layer to the buried diffusion layer, and the increased encroachment of the buried diffusion oxide, can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

摘要翻译： 一种用于制造浮动栅极存储器件的方法，包括使用较薄的掩埋扩散区，其中埋入扩散氧化物层的埋入扩大到掩埋扩散层内并在浮动栅极下方的隧道氧化物下面。 此外，浮置栅极多晶硅层具有比掩埋扩散高度更大的高度。 栅极多晶硅层对掩埋扩散层的阶梯高度增加以及掩埋扩散氧化物的侵蚀增加，可以产生较高的GCR，同时仍然允许使用虚拟接地阵列设计减小电池尺寸。

公开(公告)号：US08927370B2

公开(公告)日：2015-01-06

申请号：US11459416

申请日：2006-07-24

申请人： Chun-Yuan Lo ,  Chun-Pei Wu

发明人： Chun-Yuan Lo ,  Chun-Pei Wu

IPC分类号： H01L21/8234 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in the substrate adjacent to the sides of the first conductive layer. An inter-gate dielectric layer is then formed over the first conductive layer followed by forming a second conductive layer over the inter-gate dielectric layer. A transistor gate is subsequently formed over the gate insulating layer in the periphery area.

摘要翻译： 提供一种用于制造具有存储区域和周边区域的存储器的方法。 该方法包括在周边区域的基板上形成栅极绝缘层。 此后，在存储区域中形成第一导电层，随后在与第一导电层的侧面相邻的衬底中形成掩埋扩散区域。 然后在第一导电层之上形成栅极间电介质层，随后在栅极间电介质层上形成第二导电层。 随后在周边区域中的栅极绝缘层上形成晶体管栅极。

公开(公告)号：US20070264774A1

公开(公告)日：2007-11-15

申请号：US11383073

申请日：2006-05-12

申请人： Tian-Shuan Luo ,  Chun-Pei Wu

发明人： Tian-Shuan Luo ,  Chun-Pei Wu

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A method of manufacturing a flash memory device having an enhanced gate coupling ratio includes steps of forming a first semiconductor layer on a substrate and forming a semiconductor spacer layer on top of the first semiconductor layer. The semiconductor spacer layer includes a plurality of recesses. The method provides a semiconductor spacer structure which functions to increase the contact area between a floating gate and a control gate of the flash memory device.

摘要翻译： 具有增强的栅极耦合比的闪存器件的制造方法包括在衬底上形成第一半导体层并在第一半导体层顶部形成半导体间隔层的步骤。 半导体间隔层包括多个凹部。 该方法提供半导体间隔结构，其用于增加闪存器件的浮动栅极和控制栅极之间的接触面积。

公开(公告)号：US20070259496A1

公开(公告)日：2007-11-08

申请号：US11417791

申请日：2006-05-03

申请人： Hsin-Fu Lin ,  Chun-Pei Wu

发明人： Hsin-Fu Lin ,  Chun-Pei Wu

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/76202 ,  H01L27/11521

摘要： A method for fabricating a non-volatile memory is provided. A dielectric layer, a first conductive layer, and a mask layer are formed sequentially on a substrate and then patterned to form a number of openings and floating gates. In addition, spacers are formed on the sidewalls of the openings. A source/drain region is formed in the substrate underneath each of the openings. A thermal process is performed to oxidize the substrate exposed by the opening to form an insulating layer above the source/drain region. Afterward, the mask layer is removed and an inter-gate dielectric layer is formed to cover the surface of the first conductive layer and the surface of the insulating layer. Subsequently, a second conductive layer is formed on the inter-gate dielectric layer.

摘要翻译： 提供了一种用于制造非易失性存储器的方法。 依次在基板上形成电介质层，第一导电层和掩模层，然后将其图案化以形成多个开口和浮动栅极。 此外，在开口的侧壁上形成间隔物。 源极/漏极区域形成在每个开口下方的衬底中。 进行热处理以氧化由开口暴露的衬底，以在源极/漏极区域上方形成绝缘层。 之后，去除掩模层，并形成栅极间电介质层以覆盖第一导电层的表面和绝缘层的表面。 随后，在栅极间电介质层上形成第二导电层。

公开(公告)号：US20060284267A1

公开(公告)日：2006-12-21

申请号：US11157303

申请日：2005-06-20

申请人： Hsin-Fu Lin ,  Chun-Pei Wu

发明人： Hsin-Fu Lin ,  Chun-Pei Wu

IPC分类号： H01L29/76 ,  H01L21/8236

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A flash memory comprises a substrate, control gates, doped regions, an isolation layer, isolation structures, floating gates, tunneling dielectric layers and inter-gate dielectric layers. The control gates are arranged over the substrate with a first direction, and the doped regions are arranged within the substrate with a second direction. The isolation layers are disposed between the control gates and the doping regions, and the isolation structures are disposed within the substrate where the doped regions and the control gates do not overlap. Furthermore, the floating gates are disposed between the control gates and the substrate that is not covered by the isolation layers. The tunneling dielectric layers are disposed between the substrate and the floating gates. The inter-gate dielectric layers are disposed between the control gates and the floating gates.

摘要翻译： 闪速存储器包括衬底，控制栅极，掺杂区域，隔离层，隔离结构，浮置栅极，隧道电介质层和栅极间电介质层。 控制栅极以第一方向布置在衬底上，并且掺杂区域以第二方向布置在衬底内。 隔离层设置在控制栅极和掺杂区域之间，并且隔离结构设置在衬底内，其中掺杂区域和控制栅极不重叠。 此外，浮动栅极设置在控制栅极和未被隔离层覆盖的衬底之间。 隧道电介质层设置在衬底和浮动栅极之间。 栅极间电介质层设置在控制栅极和浮栅之间。

公开(公告)号：US08300462B2

公开(公告)日：2012-10-30

申请号：US13367122

申请日：2012-02-06

申请人： Chun-Pei Wu ,  Chia-Ta Shieh ,  Chih-Wei Hung ,  Mars Chen

发明人： Chun-Pei Wu ,  Chia-Ta Shieh ,  Chih-Wei Hung ,  Mars Chen

IPC分类号： G11C16/04

CPC分类号： G11C16/0416 ,  G11C16/0433 ,  H01L27/11565 ,  H01L27/11568

摘要： A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage.

摘要翻译： 一种方法包括对电可擦除可编程只读存储器（EEPROM）阵列执行操作。 从程序操作和擦除操作中选择操作。 EEPROM阵列包括排列成行和列的EEPROM单元，以及沿列方向延伸的多个字线。 多个字线中的每一个连接到同一列中的EEPROM单元的控制栅极。 EEPROM阵列还包括沿行方向延伸的多个源极线。 多个源极线中的每一个连接到同一行中的EEPROM单元的源极。 在操作期间，多个源极线中的第一源极线被施加第一源极线电压，并且多个源极线中的第二源极线施加与第二源极线不同的第二源极线电压 第一源线电压。

公开(公告)号：US20120134209A1

公开(公告)日：2012-05-31

申请号：US13367122

申请日：2012-02-06

申请人： Chun-Pei Wu ,  Chia-Ta Shieh ,  Chih-Wei Hung ,  Mars Chen

发明人： Chun-Pei Wu ,  Chia-Ta Shieh ,  Chih-Wei Hung ,  Mars Chen

IPC分类号： G11C16/04

CPC分类号： G11C16/0416 ,  G11C16/0433 ,  H01L27/11565 ,  H01L27/11568

摘要： A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage.

摘要翻译： 一种方法包括对电可擦除可编程只读存储器（EEPROM）阵列执行操作。 从程序操作和擦除操作中选择操作。 EEPROM阵列包括排列成行和列的EEPROM单元，以及沿列方向延伸的多个字线。 多个字线中的每一个连接到同一列中的EEPROM单元的控制栅极。 EEPROM阵列还包括沿行方向延伸的多个源极线。 多个源极线中的每一个连接到同一行中的EEPROM单元的源极。 在操作期间，多个源极线中的第一源极线被施加第一源极线电压，并且多个源极线中的第二源极线施加与第二源极线不同的第二源极线电压 第一源线电压。

公开(公告)号：US07384848B2

公开(公告)日：2008-06-10

申请号：US11281928

申请日：2005-11-18

申请人： Chun-Pei Wu ,  Wei-Ming Chung ,  Huei-Huarng Chen

发明人： Chun-Pei Wu ,  Wei-Ming Chung ,  Huei-Huarng Chen

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method for forming a non-volatile memory with inlaid floating gate is disclosed. The method comprises the following steps. A substrate having a pad dielectric layer and a first dielectric layer thereon is provided. Then a buried diffusion region is formed in the substrate. Next a second dielectric layer is formed over the substrate and the second dielectric layer and the pad dielectric layer are then etched back to expose the buried diffusion region and the first dielectric layer. Then a shallow trench isolation is formed into the expose the buried diffusion region and the substrate. Next a floating gate pattern is transferred into the first and second dielectric layers. Next the first dielectric layer is removed to expose the pad dielectric layer. Then the exposed pad dielectric layer is removed to expose the substrate. Next a tunnel dielectric layer is formed on the exposed substrate. Next a first conductive layer is conformally formed over the substrate and is planarized to expose the shallow trench isolation. Then an inter gate dielectric layer is formed over the first conductive layer and the shallow trench isolation. Finally a second conductive layer is formed over the inter gate dielectric layer.

摘要翻译： 公开了一种用嵌入式浮动栅极形成非易失性存储器的方法。 该方法包括以下步骤。 提供了具有焊盘电介质层和其上的第一电介质层的衬底。 然后在衬底中形成掩埋扩散区。 接下来，在衬底上形成第二电介质层，然后将第二电介质层和焊盘电介质层回蚀刻以暴露掩埋扩散区域和第一介电层。 然后形成浅沟槽隔离，将掩埋的扩散区域和衬底暴露。 接下来，浮置栅极图案被转移到第一和第二电介质层中。 接下来，去除第一介电层以露出焊盘介电层。 然后去除暴露的焊盘介电层以露出衬底。 接下来，在暴露的基板上形成隧道介电层。 接下来，第一导电层保形地形成在衬底上并且被平坦化以暴露浅沟槽隔离。 然后在第一导电层和浅沟槽隔离件之上形成栅极介电层。 最后，在栅极间介电层上形成第二导电层。

公开(公告)号：US20080020525A1

公开(公告)日：2008-01-24

申请号：US11459416

申请日：2006-07-24

申请人： Chun-Yuan Lo ,  Chun-Pei Wu

发明人： Chun-Yuan Lo ,  Chun-Pei Wu

IPC分类号： H01L21/8234

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in the substrate adjacent to the sides of the first conductive layer. An inter-gate dielectric layer is then formed over the first conductive layer followed by forming a second conductive layer over the inter-gate dielectric layer. A transistor gate is subsequently formed over the gate insulating layer in the periphery area.

摘要翻译： 提供一种用于制造具有存储区域和周边区域的存储器的方法。 该方法包括在周边区域的基板上形成栅极绝缘层。 此后，在存储区域中形成第一导电层，随后在与第一导电层的侧面相邻的衬底中形成掩埋扩散区域。 然后在第一导电层之上形成栅极间电介质层，随后在栅极间电介质层上形成第二导电层。 随后在周边区域中的栅极绝缘层上形成晶体管栅极。