公开(公告)号：US08106512B2

公开(公告)日：2012-01-31

申请号：US12845852

申请日：2010-07-29

申请人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

发明人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/53238 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.

摘要翻译： 上述结构和方法提供了提高互连可靠性和电阻率的机制。 通过使用复合阻挡层来提高互连的可靠性和电阻率，该复合阻挡层提供良好的台阶覆盖率，良好的铜扩散阻挡层和与相邻层的良好粘附性。 复合阻挡层包括ALD阻挡层以提供良好的阶梯覆盖。 复合阻挡层还包括至少包含含有Mn，Cr，V，Ti或Nb的元素或化合物以提高粘合性的阻隔增粘膜。 复合阻挡层还可以包括在ALD阻挡层和阻挡增粘层之间的Ta或Ti层。

公开(公告)号：US07651943B2

公开(公告)日：2010-01-26

申请号：US12032968

申请日：2008-02-18

申请人： Chen-Hua Yu ,  Ming Han Lee ,  Ming-Shih Yeh

发明人： Chen-Hua Yu ,  Ming Han Lee ,  Ming-Shih Yeh

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an interconnect structure of an integrated circuit includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; and forming a copper alloy seed layer in the opening. The copper alloy seed layer physically contacts the dielectric layer. The copper alloy seed layer includes copper and an alloying material. The method further includes filling a metallic material in the opening and over the copper alloy seed layer; performing a planarization to remove excess metallic material over the dielectric layer; and performing a thermal anneal to cause the alloying material in the copper alloy seed layer to be segregated from copper.

摘要翻译： 形成集成电路的互连结构的方法包括提供半导体衬底; 在所述半导体衬底上形成介电层; 在介电层中形成开口; 并在开口中形成铜合金种子层。 铜合金种子层物理接触介电层。 铜合金种子层包括铜和合金材料。 该方法还包括将金属材料填充在铜合金种子层的开口中和上方; 执行平坦化以在电介质层上除去多余的金属材料; 并进行热退火以使铜合金种子层中的合金材料与铜分离。

公开(公告)号：US20090209099A1

公开(公告)日：2009-08-20

申请号：US12032968

申请日：2008-02-18

申请人： Chen-Hua Yu ,  Ming Han Lee ,  Ming-Shih Yeh

发明人： Chen-Hua Yu ,  Ming Han Lee ,  Ming-Shih Yeh

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an interconnect structure of an integrated circuit includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; and forming a copper alloy seed layer in the opening. The copper alloy seed layer physically contacts the dielectric layer. The copper alloy seed layer includes copper and an alloying material. The method further includes filling a metallic material in the opening and over the copper alloy seed layer; performing a planarization to remove excess metallic material over the dielectric layer; and performing a thermal anneal to cause the alloying material in the copper alloy seed layer to be segregated from copper.

摘要翻译： 形成集成电路的互连结构的方法包括提供半导体衬底; 在所述半导体衬底上形成介电层; 在介电层中形成开口; 并在开口中形成铜合金种子层。 铜合金种子层物理接触介电层。 铜合金种子层包括铜和合金材料。 该方法还包括将金属材料填充在铜合金种子层的开口中和上方; 执行平坦化以在电介质层上除去多余的金属材料; 并进行热退火以使铜合金种子层中的合金材料与铜分离。

公开(公告)号：US20110024908A1

公开(公告)日：2011-02-03

申请号：US12845852

申请日：2010-07-29

申请人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

发明人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.

摘要翻译： 上述结构和方法提供了提高互连可靠性和电阻率的机制。 通过使用复合阻挡层来提高互连的可靠性和电阻率，该复合阻挡层提供良好的台阶覆盖率，良好的铜扩散阻挡层和与相邻层的良好粘附性。 复合阻挡层包括ALD阻挡层以提供良好的阶梯覆盖。 复合阻挡层还包括至少包含含有Mn，Cr，V，Ti或Nb的元素或化合物以提高粘合性的阻隔增粘膜。 复合阻挡层还可以包括在ALD阻挡层和阻挡增粘层之间的Ta或Ti层。

公开(公告)号：US20090218693A1

公开(公告)日：2009-09-03

申请号：US12112405

申请日：2008-04-30

申请人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu

发明人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L23/485 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor contact structure includes a copper plug formed within a dual damascene, single damascene or other opening formed in a dielectric material and includes a composite barrier layer between the copper plug and the sidewalls and bottom of the opening. The composite barrier layer preferably includes an ALD TaN layer disposed on the bottom and along the sides of the opening although other suitable ALD layers may be used. A barrier material is disposed between the copper plug and the ALD layer. The barrier layer may be a Mn-based barrier layer, a Cr-based barrier layer, a V-based barrier layer, a Nb-based barrier layer, a Ti-based barrier layer, or other suitable barrier layers.

摘要翻译： 半导体接触结构包括形成在双镶嵌，单镶嵌或形成在电介质材料中的其它开口的铜塞，并且包括铜塞与开口的侧壁和底部之间的复合阻挡层。 复合阻挡层优选地包括设置在开口的底部和沿着开口的侧面的ALD TaN层，尽管可以使用其它合适的ALD层。 阻挡材料设置在铜塞和ALD层之间。 阻挡层可以是基于Mn的阻挡层，Cr基阻挡层，V基阻挡层，Nb基阻挡层，Ti基阻挡层或其它合适的阻挡层。

公开(公告)号：US20090117731A1

公开(公告)日：2009-05-07

申请号：US11934005

申请日：2007-11-01

申请人： Chen-Hua Yu ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Ming-Shih Yeh ,  Ming-Han Lee

发明人： Chen-Hua Yu ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Ming-Shih Yeh ,  Ming-Han Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2221/1089

摘要： A semiconductor interconnection structure is manufactured as follows. First, a substrate with a first dielectric layer and a second dielectric layer is formed. Subsequently, an opening is formed in the second dielectric layer. A thin metal layer and a seed layer are formed in sequence on the surface of the second dielectric layer in the opening, wherein the metal layer comprises at least one metal species having phase segregation property of a second conductor. The wafer of the substrate is subjected to a thermal treatment, by which most of the metal species in the metal layer at a bottom of the opening is diffused to a top surface of the second conductor to form a metal-based oxide layer. Afterwards, the wafer is subjected to planarization, so as to remove the second conductor outside the opening.

摘要翻译： 如下制造半导体互连结构。 首先，形成具有第一介电层和第二介质层的基板。 随后，在第二电介质层中形成开口。 在开口中的第二电介质层的表面上依次形成薄金属层和种子层，其中金属层包含至少一种具有第二导体的相分离特性的金属物质。 对基板的晶片进行热处理，通过该热处理，开口底部的金属层中的大部分金属物质扩散到第二导体的顶表面，形成金属基氧化物层。 然后，对晶片进行平面化处理，以便将开口外的第二导体移除。

公开(公告)号：US08013445B2

公开(公告)日：2011-09-06

申请号：US12112405

申请日：2008-04-30

申请人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu

发明人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L23/485 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor contact structure includes a copper plug formed within a dual damascene, single damascene or other opening formed in a dielectric material and includes a composite barrier layer between the copper plug and the sidewalls and bottom of the opening. The composite barrier layer preferably includes an ALD TaN layer disposed on the bottom and along the sides of the opening although other suitable ALD layers may be used. A barrier material is disposed between the copper plug and the ALD layer. The barrier layer may be a Mn-based barrier layer, a Cr-based barrier layer, a V-based barrier layer, a Nb-based barrier layer, a Ti-based barrier layer, or other suitable barrier layers.

摘要翻译： 半导体接触结构包括形成在双镶嵌，单镶嵌或形成在电介质材料中的其它开口的铜塞，并且包括铜塞与开口的侧壁和底部之间的复合阻挡层。 复合阻挡层优选地包括设置在开口的底部和侧面上的ALD TaN层，尽管可以使用其它合适的ALD层。 阻挡材料设置在铜塞和ALD层之间。 阻挡层可以是基于Mn的阻挡层，Cr基阻挡层，V基阻挡层，Nb基阻挡层，Ti基阻挡层或其它合适的阻挡层。

公开(公告)号：US08623760B2

公开(公告)日：2014-01-07

申请号：US13440704

申请日：2012-04-05

申请人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

发明人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

IPC分类号： H01L21/768

CPC分类号： H01L21/76849 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76865 ,  H01L21/76883

摘要： An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.

摘要翻译： 集成电路包括半导体衬底，半导体衬底上的低k电介质层，低k电介质层中的第一开口，第一开口中的第一扩散阻挡层，覆盖第一开口中的低k电介质层 开口，其中所述第一扩散阻挡层具有连接到侧壁部分的底部，并且其中所述侧壁部分具有靠近所述低k电介质层的顶表面的顶表面。 集成电路还包括填充第一开口的导电线，其中导电线具有比扩散阻挡层的侧壁部分的顶表面低的顶表面，以及导电线上的金属盖，并且仅在直接在 导线。

公开(公告)号：US08193087B2

公开(公告)日：2012-06-05

申请号：US11605893

申请日：2006-11-28

申请人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

发明人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

IPC分类号： H01L21/768

CPC分类号： H01L21/76849 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76865 ,  H01L21/76883

摘要： An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.

摘要翻译： 集成电路包括半导体衬底，半导体衬底上的低k电介质层，低k电介质层中的第一开口，第一开口中的第一扩散阻挡层，覆盖第一开口中的低k电介质层 开口，其中所述第一扩散阻挡层具有连接到侧壁部分的底部，并且其中所述侧壁部分具有靠近所述低k电介质层的顶表面的顶表面。 集成电路还包括填充第一开口的导电线，其中导电线具有比扩散阻挡层的侧壁部分的顶表面低的顶表面，以及导电线上的金属盖，并且仅在直接在 导线。

公开(公告)号：US20070269978A1

公开(公告)日：2007-11-22

申请号：US11605893

申请日：2006-11-28

申请人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

发明人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

IPC分类号： H01L21/768

CPC分类号： H01L21/76849 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76865 ,  H01L21/76883

摘要： An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.

摘要翻译： 集成电路包括半导体衬底，半导体衬底上的低k电介质层，低k电介质层中的第一开口，第一开口中的第一扩散阻挡层，覆盖第一开口中的低k电介质层 开口，其中所述第一扩散阻挡层具有连接到侧壁部分的底部，并且其中所述侧壁部分具有靠近所述低k电介质层的顶表面的顶表面。 集成电路还包括填充第一开口的导电线，其中导电线具有比扩散阻挡层的侧壁部分的顶表面低的顶表面，以及导电线上的金属盖，并且仅在直接在 导线。