公开(公告)号：US07951670B2

公开(公告)日：2011-05-31

申请号：US11368714

申请日：2006-03-06

申请人： Chen-Ming Huang ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chang-Jen Hsieh ,  Ya-Chen Kao

发明人： Chen-Ming Huang ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chang-Jen Hsieh ,  Ya-Chen Kao

IPC分类号： H01L21/336

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

摘要： A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap layer is disposed on the floating gate. A control gate is disposed over the sidewall of the floating gate and insulated therefrom, partially extending to the upper surface of the cap layer. A source region is formed in the substrate near one side of the floating gate.

摘要翻译： 分离门存储单元。 浮置栅极设置在基板上并与基板绝缘，该基板包括由形成在其中的一对隔离结构分开的有源区域。 浮栅设置在一对隔离结构之间，并且不与其上表面重叠。 盖层设置在浮动栅上。 控制栅极设置在浮动栅极的侧壁上并与其绝缘，部分地延伸到盖层的上表面。 源极区域形成在靠近浮动栅极一侧的衬底中。

公开(公告)号：US20080121975A1

公开(公告)日：2008-05-29

申请号：US11592290

申请日：2006-11-03

申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.

摘要翻译： 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。 一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。 一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

公开(公告)号：US20080105917A1

公开(公告)日：2008-05-08

申请号：US11785382

申请日：2007-04-17

申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC分类号： H01L29/788 ,  H01L27/115

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.

摘要翻译： 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，两个相邻的隔离区域限定具有一对漏极和源极区域的有源区域。 活动区域的顶层低于隔离区域的顶层。 一对浮置栅极设置在有源区上并与隔离区对准，其中钝化层设置在浮栅上以防止CMP变薄。 一对控制栅极与浮动栅极自对准，并沿第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

公开(公告)号：US07667261B2

公开(公告)日：2010-02-23

申请号：US11785382

申请日：2007-04-17

申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.

摘要翻译： 分离栅存储单元及其制造方法。 分离栅存储器单元包括沿着第一方向在半导体衬底上形成的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。 活动区域的顶层低于隔离区域的顶层。 一对浮置栅极设置在有源区上并与隔离区对准，其中钝化层设置在浮栅上以防止CMP变薄。 一对控制栅极与浮动栅极自对准，并沿第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

公开(公告)号：US07652318B2

公开(公告)日：2010-01-26

申请号：US11592290

申请日：2006-11-03

申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.

摘要翻译： 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，两个相邻的隔离区域限定具有一对漏极和源极区域的有源区域。 一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。 一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

公开(公告)号：US20070205436A1

公开(公告)日：2007-09-06

申请号：US11368714

申请日：2006-03-06

申请人： Chen-Ming Huang ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chang-Jen Hsieh ,  Ya-Chen Kao

发明人： Chen-Ming Huang ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chang-Jen Hsieh ,  Ya-Chen Kao

IPC分类号： H01L29/76

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

摘要： A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap layer is disposed on the floating gate. A control gate is disposed over the sidewall of the floating gate and insulated therefrom, partially extending to the upper surface of the cap layer. A source region is formed in the substrate near one side of the floating gate.

摘要翻译： 分离门存储单元。 浮置栅极设置在基板上并与基板绝缘，该基板包括由形成在其中的一对隔离结构分开的有源区域。 浮栅设置在一对隔离结构之间，并且不与其上表面重叠。 盖层设置在浮动栅上。 控制栅极设置在浮动栅极的侧壁上并与其绝缘，部分地延伸到盖层的上表面。 源极区域形成在靠近浮动栅极一侧的衬底中。

公开(公告)号：US06649489B1

公开(公告)日：2003-11-18

申请号：US10366207

申请日：2003-02-13

申请人： Li-Wen Chang ,  Hung-Cheng Sung ,  Der-Shin Shyu ,  Han-Ping Chen ,  Chen-Ming Huang ,  Ya-Chen Kao

发明人： Li-Wen Chang ,  Hung-Cheng Sung ,  Der-Shin Shyu ,  Han-Ping Chen ,  Chen-Ming Huang ,  Ya-Chen Kao

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： A method of etch polysilicon adjacent to a recessed STI structure feature is described. A substrate is provided with a dielectric layer thereon and a polysilicon layer on the dielectric layer. A shallow trench is formed that extends through the polysilicon and dielectric layers into the substrate. An insulating material is used to fill the trench and is then recessed in the trench below the surface of the substrate by polishing and etching steps. A conformal buffer layer is deposited which covers the polysilicon and sidewalls of the trench above the recessed insulating layer. The buffer layer is etched back to expose the insulating layer and the polysilicon is removed by a plasma etch. A spacer comprised of a portion of the buffer layer protects the substrate during the polysilicon etch to prevent unwanted trenches from being formed adjacent to the STI structure, thereby increasing the etch process window.

摘要翻译： 描述了与凹陷STI结构特征相邻的蚀刻多晶硅的方法。 衬底上设置介电层，并在电介质层上设置多晶硅层。 形成浅沟槽，其延伸穿过多晶硅和电介质层进入衬底。 绝缘材料用于填充沟槽，然后通过抛光和蚀刻步骤将其凹入到衬底表面下方的沟槽中。 沉积保形缓冲层，其覆盖凹陷绝缘层上方的沟槽的多晶硅和侧壁。 将缓冲层回蚀刻以暴露绝缘层，并且通过等离子体蚀刻去除多晶硅。 由缓冲层的一部分构成的间隔件在多晶硅蚀刻期间保护衬底以防止在STI结构附近形成不必要的沟槽，从而增加蚀刻工艺窗口。

公开(公告)号：US06819593B2

公开(公告)日：2004-11-16

申请号：US10318458

申请日：2002-12-13

申请人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Li-Wen Chang ,  Han-Ping Chen ,  Chen-Ming Huang ,  Ya-Chen Kao

发明人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Li-Wen Chang ,  Han-Ping Chen ,  Chen-Ming Huang ,  Ya-Chen Kao

IPC分类号： G11C1600

CPC分类号： G11C16/3418 ,  G11C16/0425

摘要： A method to suppress bit-line leakage in a nonvolatile memory cell is achieved. The method comprises providing an array of nonvolatile memory cells comprising source and bulk terminals. The array comprises a plurality of subarrays. The sources of all the nonvolatile cells in each subarray are coupled together to form a common subarray source. Bulks of all the nonvolatile cells in the array are coupled together to form a common array bulk. A first, non-zero voltage is forced between the common subarray source and the common array bulk for a first subarray that is selected for an access operation. A second, non-zero voltage is forced between the common subarray source and the common array bulk for a second subarray that is not selected for an access operation. The second, non-zero voltage inhibits bit line leakage in the second subarray.

摘要翻译： 实现了在非易失性存储单元中抑制位线泄漏的方法。 该方法包括提供包括源极和体积端子的非易失性存储器单元的阵列。 阵列包括多个子阵列。 每个子阵列中的所有非易失性单元的源耦合在一起以形成公共的子阵列源。 阵列中所有非易失性单元的容量被耦合在一起以形成共同的阵列体。 对于为访问操作选择的第一子阵列，第一个非零电压被强制在公共子阵列源和公共阵列块之间。 第二个非零电压被强制在公共子阵列源和公共阵列块之间，用于未被选择用于访问操作的第二子阵列。 第二个非零电压禁止第二个子阵列中的位线泄漏。

公开(公告)号：US07326994B2

公开(公告)日：2008-02-05

申请号：US11248357

申请日：2005-10-12

申请人： Te-Hsun Hsu ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Shih-Wei Wang

发明人： Te-Hsun Hsu ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Shih-Wei Wang

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11558

摘要： A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a semiconductor substrate, a floating gate over the semiconductor substrate, a first, a second, and a third capacitor each having a first plate and sharing a common floating gate as a second plate. The non-volatile memory cell further includes a transistor connected in series with the first capacitor. The gate electrode of the transistor is connected to a wordline of a memory array, and a source/drain region is connected to a bitline.

摘要翻译： 提供了一种非易失性存储单元及其制造方法。 非易失性存储单元包括半导体衬底，半导体衬底上的浮置栅极，第一，第二和第三电容器，每个电容器具有第一板并且共用公共浮置栅极作为第二板。 非易失性存储单元还包括与第一电容器串联连接的晶体管。 晶体管的栅电极连接到存储器阵列的字线，源极/漏极区连接到位线。

公开(公告)号：US06312989B1

公开(公告)日：2001-11-06

申请号：US09489496

申请日：2000-01-21

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell. The vertical orientation of the source structure and the floating gate and the self-alignment of the spacer control gate to the floating gate together makes it possible to reduce the memory cell substantially.

摘要翻译： 公开了一种用于形成具有突出源的分裂栅极闪存单元来代替常规扁平源的方法。 垂直突出的源结构具有顶部和底部。 底部是多晶硅，而顶部是多晶氧化物。 源极上的突出结构的垂直壁用于形成具有中间栅极氧化物的垂直浮动栅极和间隔物控制栅极。 因为现在通过垂直壁提供源极和浮动栅极之间的耦合，所以耦合面积比常规扁平源大得多。 此外，不再存在源极和漏极之间的电压穿通的问题。 垂直浮动栅极也变薄，使得所得到的薄而尖锐的多尖端进一步增强了闪存单元的擦除和编程速度。 源结构和浮置栅极的垂直取向以及间隔物控制栅极与浮置栅极的自对准一起使得可以基本上减小存储单元。