公开(公告)号：US07557402B2

公开(公告)日：2009-07-07

申请号：US11599930

申请日：2006-11-15

申请人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

发明人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

IPC分类号： H01L29/34

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

摘要翻译： 一种嵌入式闪存单元结构，其包括结构，第一浮动栅极，其具有在所述结构上方的暴露侧壁，第二浮动栅极，具有在所述结构上并与所述第一浮动栅极间隔开的暴露的侧壁; 相应的第一浮动栅极和第二浮动栅极，至少在第一和第二浮动栅极的相应暴露的侧壁上方的第二对间隔物，在第二对间隔物之间​​的结构中的源极区域，源极植入物 并且设置在第一对间隔件外侧的第一和第二控制门，并且暴露在结构的暴露的外侧部分中的结构的外侧部分和相应的漏极区域。 还提供了一种形成嵌入式闪存单元结构的方法。

公开(公告)号：US20070063248A1

公开(公告)日：2007-03-22

申请号：US11599930

申请日：2006-11-15

申请人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

发明人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

摘要翻译： 一种嵌入式闪存单元结构，其包括结构，第一浮动栅极，其具有在所述结构上方的暴露侧壁，第二浮动栅极，具有在所述结构上并与所述第一浮动栅极间隔开的暴露的侧壁; 相应的第一浮动栅极和第二浮动栅极，至少在第一和第二浮动栅极的相应暴露的侧壁上方的第二对间隔物，在第二对间隔物之间​​的结构中的源极区域，源极植入物 并且设置在第一对间隔件外侧的第一和第二控制门，并且暴露在结构的暴露的外侧部分中的结构的外侧部分和相应的漏极区域。 还提供了一种形成嵌入式闪存单元结构的方法。

公开(公告)号：US06878986B2

公开(公告)日：2005-04-12

申请号：US10403137

申请日：2003-03-31

申请人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

发明人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A memory cell including a substrate having a source region; a floating gate structure disposed over the substrate and associated with the source region; and a source coupling enhancement structure covering an exposed portion of the floating gate structure and extending to the source region. The flash memory cell can be fabricated in a method including the steps of forming the floating gate structure over a substrate; forming the source coupling enhancement structure on an exposed portion of the floating gate structure; and forming the source region in the substrate.

摘要翻译： 一种存储单元，包括具有源极区域的衬底; 浮置栅极结构，设置在所述衬底上并与所述源极区域相关联; 以及源耦合增强结构，其覆盖所述浮栅结构的暴露部分并延伸到所述源极区。 闪存单元可以以包括以下步骤的方法制造：在衬底上形成浮置栅极结构; 在所述浮动栅极结构的暴露部分上形成所述源耦合增强结构; 以及在衬底中形成源区。

公开(公告)号：US06649489B1

公开(公告)日：2003-11-18

申请号：US10366207

申请日：2003-02-13

申请人： Li-Wen Chang ,  Hung-Cheng Sung ,  Der-Shin Shyu ,  Han-Ping Chen ,  Chen-Ming Huang ,  Ya-Chen Kao

发明人： Li-Wen Chang ,  Hung-Cheng Sung ,  Der-Shin Shyu ,  Han-Ping Chen ,  Chen-Ming Huang ,  Ya-Chen Kao

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： A method of etch polysilicon adjacent to a recessed STI structure feature is described. A substrate is provided with a dielectric layer thereon and a polysilicon layer on the dielectric layer. A shallow trench is formed that extends through the polysilicon and dielectric layers into the substrate. An insulating material is used to fill the trench and is then recessed in the trench below the surface of the substrate by polishing and etching steps. A conformal buffer layer is deposited which covers the polysilicon and sidewalls of the trench above the recessed insulating layer. The buffer layer is etched back to expose the insulating layer and the polysilicon is removed by a plasma etch. A spacer comprised of a portion of the buffer layer protects the substrate during the polysilicon etch to prevent unwanted trenches from being formed adjacent to the STI structure, thereby increasing the etch process window.

摘要翻译： 描述了与凹陷STI结构特征相邻的蚀刻多晶硅的方法。 衬底上设置介电层，并在电介质层上设置多晶硅层。 形成浅沟槽，其延伸穿过多晶硅和电介质层进入衬底。 绝缘材料用于填充沟槽，然后通过抛光和蚀刻步骤将其凹入到衬底表面下方的沟槽中。 沉积保形缓冲层，其覆盖凹陷绝缘层上方的沟槽的多晶硅和侧壁。 将缓冲层回蚀刻以暴露绝缘层，并且通过等离子体蚀刻去除多晶硅。 由缓冲层的一部分构成的间隔件在多晶硅蚀刻期间保护衬底以防止在STI结构附近形成不必要的沟槽，从而增加蚀刻工艺窗口。

公开(公告)号：US07056791B2

公开(公告)日：2006-06-06

申请号：US10859125

申请日：2004-06-03

申请人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang ,  Hsui Ouyang

发明人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang ,  Hsui Ouyang

IPC分类号： H01L21/8247

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546 ,  Y10S438/981

摘要： A method of fabricating an embedded flash memory device. A substrate having a memory area is provided. A device is formed on the substrate in the memory area. A conductive layer is formed over the substrate to cover the device in the memory area. A conformal insulating layer is formed on the conductive layer and the substrate. The insulating layer is removed at an edge of the memory area. By anisotropic etching, the insulating layer and part of the conductive layer is removed to form a control gate on the sidewall of the device. Thus, polysilicon residue caused by the conventional control gate process does not occur.

摘要翻译： 一种制造嵌入式闪存器件的方法。 提供具有存储区域的衬底。 在存储区域中的衬底上形成器件。 导电层形成在衬底上以覆盖存储区域中的器件。 在导电层和基板上形成保形绝缘层。 绝缘层在存储区域的边缘被去除。 通过各向异性蚀刻，去除绝缘层和导电层的一部分以在器件的侧壁上形成控制栅极。 因此，不会发生由常规控制栅极处理引起的多晶硅残渣。

公开(公告)号：US07176083B2

公开(公告)日：2007-02-13

申请号：US10870774

申请日：2004-06-17

申请人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

发明人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

公开(公告)号：US20060203537A1

公开(公告)日：2006-09-14

申请号：US11078171

申请日：2005-03-11

申请人： Hung-Cheng Sung ,  Der-Shin Shyu

发明人： Hung-Cheng Sung ,  Der-Shin Shyu

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： Methods for determining writing current for memory cells. A first reference current is applied to a first operative line to switch the memory cell to a first state. A second reference current is applied to a second operative line crossing the first operative line to switch the memory cell to a second state. A first writing current is obtained according to a first ratio and the first reference current. A second writing current is obtained according to a second ratio and the second reference current. The memory cell is programmed by applying the first writing current to the first operative line and applying the second writing current to the second operative line.

摘要翻译： 确定存储单元写入电流的方法。 将第一参考电流施加到第一操作线以将存储器单元切换到第一状态。 第二参考电流被施加到穿过第一操作线的第二操作线，以将存储器单元切换到第二状态。 根据第一比率和第一参考电流获得第一写入电流。 根据第二比例和第二参考电流获得第二写入电流。 通过将第一写入电流施加到第一操作线并将第二写入电流施加到第二操作线来编程存储器单元。

公开(公告)号：US20050282337A1

公开(公告)日：2005-12-22

申请号：US10870774

申请日：2004-06-17

申请人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

发明人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

摘要翻译： 一种嵌入式闪存单元结构，其包括结构，第一浮动栅极，其具有在所述结构上方的暴露侧壁，第二浮动栅极，具有在所述结构上并与所述第一浮动栅极间隔开的暴露的侧壁; 相应的第一浮动栅极和第二浮动栅极，至少在第一和第二浮动栅极的相应暴露的侧壁上方的第二对间隔物，在第二对间隔物之间​​的结构中的源极区域，源极植入物 并且设置在第一对间隔件外侧的第一和第二控制门，并且暴露在结构的暴露的外侧部分中的结构的外侧部分和相应的漏极区域。 还提供了一种形成嵌入式闪存单元结构的方法。

公开(公告)号：US06819593B2

公开(公告)日：2004-11-16

申请号：US10318458

申请日：2002-12-13

申请人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Li-Wen Chang ,  Han-Ping Chen ,  Chen-Ming Huang ,  Ya-Chen Kao

发明人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Li-Wen Chang ,  Han-Ping Chen ,  Chen-Ming Huang ,  Ya-Chen Kao

IPC分类号： G11C1600

CPC分类号： G11C16/3418 ,  G11C16/0425

摘要： A method to suppress bit-line leakage in a nonvolatile memory cell is achieved. The method comprises providing an array of nonvolatile memory cells comprising source and bulk terminals. The array comprises a plurality of subarrays. The sources of all the nonvolatile cells in each subarray are coupled together to form a common subarray source. Bulks of all the nonvolatile cells in the array are coupled together to form a common array bulk. A first, non-zero voltage is forced between the common subarray source and the common array bulk for a first subarray that is selected for an access operation. A second, non-zero voltage is forced between the common subarray source and the common array bulk for a second subarray that is not selected for an access operation. The second, non-zero voltage inhibits bit line leakage in the second subarray.

摘要翻译： 实现了在非易失性存储单元中抑制位线泄漏的方法。 该方法包括提供包括源极和体积端子的非易失性存储器单元的阵列。 阵列包括多个子阵列。 每个子阵列中的所有非易失性单元的源耦合在一起以形成公共的子阵列源。 阵列中所有非易失性单元的容量被耦合在一起以形成共同的阵列体。 对于为访问操作选择的第一子阵列，第一个非零电压被强制在公共子阵列源和公共阵列块之间。 第二个非零电压被强制在公共子阵列源和公共阵列块之间，用于未被选择用于访问操作的第二子阵列。 第二个非零电压禁止第二个子阵列中的位线泄漏。

公开(公告)号：US06215697B1

公开(公告)日：2001-04-10

申请号：US09231044

申请日：1999-01-14

申请人： Tao Cheng Lu ,  Der Shin Shyu ,  Shi Xian Chen ,  Wen Jer Tsai ,  Mam Tsung Wang

发明人： Tao Cheng Lu ,  Der Shin Shyu ,  Shi Xian Chen ,  Wen Jer Tsai ,  Mam Tsung Wang

IPC分类号： G11C1604

CPC分类号： G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5625 ,  G11C2211/5634

摘要： A multi-level memory cell device and method for self-converged programming which includes a memory cell switchably coupled to a non-programmable reference cell (or dummy cell), the cells arranged in respective arrays. A current source voltage between the source node and ground of the cells is relational to the threshold voltage, so as the threshold voltage is increased, the current source voltage decreases. The threshold voltage of the dummy cell is set by a stable voltage source. The memory cell is programmed and the current source voltage of the memory cell is compared to the current source voltage of the reference cell and therefore the difference in the voltages can be used to sense convergence of the programmed cell with a target threshold level set on the reference cell. A controller is also included between the reference cell and memory cell for adjusting the threshold voltage of the dummy cell according to the gate coupling ratio of the floating gate memory cell. The controller is also used to adjust voltages for both programming and read operations. The voltage difference resulting from the sources of the memory cell and reference cell is used to provide program control signals and thereby cease programming of the memory cell when convergence has been reached.

摘要翻译： 一种用于自融合编程的多级存储单元设备和方法，其包括可切换地耦合到非可编程参考单元（或虚拟单元）的存储单元，所述单元布置在相应阵列中。 电池的源节点和地之间的电流源电压与阈值电压相关，因此阈值电压增加，电流源电压降低。 虚拟单元的阈值电压由稳定的电压源设定。 对存储单元进行编程，并将存储单元的电流源电压与参考单元的电流源电压进行比较，因此可以使用电压差来检测编程单元的收敛与在 参考细胞。 参考单元和存储单元之间还包括控制器，用于根据浮动栅极存储单元的栅极耦合比来调整虚设单元的阈值电压。 控制器也用于调节编程和读取操作的电压。 由存储器单元和参考单元的源产生的电压差用于提供程序控制信号，从而在已经达到收敛时停止存储单元的编程。