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公开(公告)号：US06963135B2
公开(公告)日：2005-11-08
申请号：US10816339
申请日：2004-03-31
IPC分类号： G11C5/04 , H01L23/31 , H01L23/538 , H01L25/065 , H01L25/10 , H01L23/34
CPC分类号： H01L23/3121 , G11C5/04 , H01L23/5388 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L2224/45144 , H01L2224/48091 , H01L2224/49171 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor package includes two substrates each having a plurality of electrical connection pads, at least one chip mounted on each of the substrates, an encapsulation body formed on each of the substrates for encapsulating the chip, and an cover for receiving the substrates and the chips therein. The chip is electrically connected to the electrical connection pads. The electrical connection pads are exposed from the cover and located on the same surface or oppositely arranged. The substrates and the cover each substantially has a rectangular shape, with a longer side of each of the substrates being vertical to a longer side of the cover. The semiconductor package is incorporated with multiple chips to enhance the performance and memory capacity thereof, and the substrates are smaller than those in the prior art and thus are more cost-effective to fabricate.
摘要翻译： 半导体封装包括两个基板，每个基板具有多个电连接焊盘，安装在每个基板上的至少一个芯片，形成在每个基板上的封装体，用于封装芯片;以及盖，用于接收基板和芯片 其中。 芯片电连接到电连接焊盘。 电连接垫从盖子露出并位于相同的表面上或相对布置。 基板和盖子基本上具有矩形形状，每个基板的较长边与盖的较长边垂直。 半导体封装结合有多个芯片以提高其性能和存储器容量，并且衬底小于现有技术中的衬底，因此制造更具成本效益。
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公开(公告)号：US20050093143A1
公开(公告)日：2005-05-05
申请号：US10816339
申请日：2004-03-31
IPC分类号： G11C5/04 , H01L23/31 , H01L23/538 , H01L25/065 , H01L25/10 , H01L23/34 , H01L23/28
CPC分类号： H01L23/3121 , G11C5/04 , H01L23/5388 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L2224/45144 , H01L2224/48091 , H01L2224/49171 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor package includes two substrates each having a plurality of electrical connection pads, at least one chip mounted on each of the substrates, an encapsulation body formed on each of the substrates for encapsulating the chip, and an cover for receiving the substrates and the chips therein. The chip is electrically connected to the electrical connection pads. The electrical connection pads are exposed from the cover and located on the same surface or oppositely arranged. The substrates and the cover each substantially has a rectangular shape, with a longer side of each of the substrates being vertical to a longer side of the cover. The semiconductor package is incorporated with multiple chips to enhance the performance and memory capacity thereof, and the substrates are smaller than those in the prior art and thus are more cost-effective to fabricate.
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公开(公告)号：USD493799S1
公开(公告)日：2004-08-03
申请号：US29195995
申请日：2003-12-18
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公开(公告)号：USD498760S1
公开(公告)日：2004-11-23
申请号：US29196558
申请日：2003-12-30
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